Subject Syllabus Hub261+ MCQs9 Topics

Computer Architecture and Organization

Comprehensive study of CPU design, instruction set architecture, memory hierarchy, cache organization, pipelining, and system bus interfaces.

Topic Syllabus & Revision Notes

High-yield concept summaries, formulas, and common exam pitfalls for each topic.

Topic 14 Key Rules

Basic Computer Organization & System Bus

Computer Organization deals with structural relationships and hardware operational units. The central processing unit (CPU) interacts with main memory and peripheral devices via system buses. The Address bus determines addressable memory locations, Data bus carries actual data payload, and Control bus regulates system timing and read/write commands.

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Topic 25 Key Rules

Computer Architecture

### Computer Architecture Core Concept Breakdown 1. **Instruction Pipelining**: Pipelining increases CPU instruction throughput by overlapping instruction execution stages (Fetch, Decode, Execute, Memory, Writeback). - **Non-Pipelined Time**: T_n = n * k * \tau - **Pipelined Time**: T_p = (k + n - 1) * \tau - **Ideal Speedup (S)**: S_k = (n * k) / (k + n - 1) -> k as n -> infinity 2. **Cache Memory & Address Structure**: - **Direct Mapping Address**: | Tag | Line / Index | Word / Offset | - **Set Associative Address**: | Tag | Set Index | Word / Offset | - **Fully Associative Address**: | Tag | Word / Offset | 3. **Cache Replacement Policies & Write Policies**: - **Write-Through**: Every write operation updates both cache and main memory. - **Write-Back**: Writes occur only in cache; main memory is updated when a dirty block is evicted.

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Topic 34 Key Rules

Computer Arithmetic, Data Representation & ALU

Computer Arithmetic covers digital representations of integer and floating-point data, alongside algorithmic operations executed by hardware adders, shifters, and multipliers inside the ALU.

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Topic 44 Key Rules

Control Unit Design & Control Logic

The Control Unit (CU) orchestrates CPU operation by emitting control signals to fetch, decode, and execute instructions. Hardwired CUs optimize for raw speed (RISC), whereas Microprogrammed CUs optimize for complex instruction sets (CISC).

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Topic 54 Key Rules

Input-Output (I/O) Organization & DMA

I/O Organization governs communication between processing elements and external peripheral devices. DMA minimizes CPU workload for bulk disk and network transfers by taking control of the system bus.

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Topic 64 Key Rules

Instruction Set Architecture & Addressing Modes

Instruction Set Architecture (ISA) serves as the interface between software and hardware. Addressing modes specify how the operational operand memory address is calculated during instruction decode stage.

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Topic 74 Key Rules

Memory Organization & Cache Memory

Memory Hierarchy optimizes speed, capacity, and cost per bit. Registers are fastest, followed by L1/L2/L3 Cache, Main Memory (DRAM), and Secondary Storage (SSD/HDD). Virtual Memory uses translation lookaside buffers (TLB) to convert virtual addresses to physical RAM frames.

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Topic 810 Key Rules

Pipelining, Flynn's Taxonomy & Parallel Processing

Instruction Pipelining increases instruction execution throughput by overlapping the execution phases (Fetch, Decode, Execute, Memory, Writeback) of multiple instructions across separate pipeline stages. While pipelining improves instruction throughput (MIPS), it does not reduce the execution latency of an individual instruction. Pipeline execution can be degraded by three major classes of hazards: Structural Hazards (resolved by separating Instruction Memory and Data Memory / Harvard Architecture), Data Hazards (resolved by Operand Forwarding or inserting 1 stall for Load-Use dependencies), and Control Hazards (mitigated by Branch Predictors, Branch Target Buffers, and Speculative Execution). Flynn's Taxonomy categorizes computer architectures based on the number of concurrent instruction and data streams: SISD, SIMD (Vector CPUs & GPUs), MISD (Fault-tolerant aerospace processors & Systolic Arrays), and MIMD (Multi-core CPUs & Distributed Clusters). Parallel Processing scaling is bounded by Amdahl's Law, which demonstrates that the sequential fraction (1 - f) strictly limits maximum speedup regardless of core count. Shared memory multiprocessors are organized as UMA (Symmetric Multiprocessing with uniform bus latency) or NUMA (Distributed main memory with localized low latency). SMT (Simultaneous Multithreading) further maximizes functional unit utilization by issuing instructions from multiple threads concurrently in a single clock cycle.

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Topic 95 Key Rules

Register Transfer & Microoperations

Registers are high-speed storage elements inside the CPU. Register Transfer Language (RTL) uses symbolic notation to describe internal CPU microoperations during instruction execution stages.

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High-Yield Practice Questions

Sample practice MCQs with step-by-step verified explanations.

Problem #1MEDIUM

कम्प्यूटर की वह सबसे छोटी इकाई जिसे वह समझता है और उस पर प्रक्रिया करता है -

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Problem #2MEDIUM

कौन सा उपकरण डाटा व प्रोग्राम के मध्य अन्तर करता है -

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Problem #3MEDIUM

निम्नलिखित में से कौन, कंट्रोल यूनिट के कार्यों का सर्वोत्तम वर्णन करता है -

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Problem #4MEDIUM

Memory में कार्यक्रम (Program) के प्रत्येक निर्देश के लिए CPU से जाता है-

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Problem #5MEDIUM

एक RAM चिप की क्षमता 8 bits(1k*8) के 1024 शब्दों की होती है। 1k*8 RAM से 16k*16 RAM बनाने के लिए आवश्यक सक्षम लाइन वाले 2x4 डिकोडर की संख्या है -

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Problem #6MEDIUM

निम्नलिखित में से कौन सी.पी.यू. (CPU) का एक घटक नहीं है -

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Problem #7MEDIUM

निम्नलिखित में से वह कौन-सी प्रणाली है, जो वास्तविक डेटा प्रोसेसिंग न करके, एक पर्यवेक्षक के रूप में, कंप्यूटर की अन्य इकाइयों के मध्य नियंत्रण और समन्वयन का कार्य करती है -

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Problem #8MEDIUM

CISC का मतलब है -

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