Computer Architecture - Revision Notes, Formulas & MCQs | UpScorer

Computer Architecture

Master Pipelining, Cache Memory Mapping, RISC vs CISC, Instruction Hazards, and Memory Hierarchy.

Concept Summary

### Computer Architecture Core Concept Breakdown 1. **Instruction Pipelining**: Pipelining increases CPU instruction throughput by overlapping instruction execution stages (Fetch, Decode, Execute, Memory, Writeback). - **Non-Pipelined Time**: T_n = n * k * \tau - **Pipelined Time**: T_p = (k + n - 1) * \tau - **Ideal Speedup (S)**: S_k = (n * k) / (k + n - 1) -> k as n -> infinity 2. **Cache Memory & Address Structure**: - **Direct Mapping Address**: | Tag | Line / Index | Word / Offset | - **Set Associative Address**: | Tag | Set Index | Word / Offset | - **Fully Associative Address**: | Tag | Word / Offset | 3. **Cache Replacement Policies & Write Policies**: - **Write-Through**: Every write operation updates both cache and main memory. - **Write-Back**: Writes occur only in cache; main memory is updated when a dirty block is evicted.

Key Revision Rules & Formulas

Pipelined Time Formula: Execution time for n instructions on a k-stage pipeline is T = (k + n - 1) * ClockCycleTime.
Pipelining Speedup Ratio: S = (n * k) / (k + n - 1). As n -> ∞, Speedup approaches k (the number of stages).
Cache Memory Placement: Direct Mapping (1 slot per block), Set Associative (N slots per set), Fully Associative (Any slot).
Pipeline Hazards: Structural (Hardware collision), Data (RAW/WAR/WAW dependencies), Control (Branch instructions).
RISC vs CISC: RISC relies on Hardwired Control and Load-Store architecture; CISC relies on Microprogrammed Control and variable instruction formats.

Common Exam Pitfalls

Confusing Pipelined execution time formula for 1 instruction vs n instructions: For 1 instruction it takes k cycles; for n instructions it takes k + n - 1 cycles.
Confusing Write-Through (updates main memory immediately) with Write-Back (uses dirty bit, updates memory on eviction).
Assuming RISC has microprogrammed control: RISC uses hardwired control for single-cycle execution.

Sample Practice Questions

Question 1: [CoA Quiz Q1/10] In a 5-stage instruction pipeline, executing 100 instructions without hazards takes how many clock cycles assuming non-pipelined execution takes 5 cycles per instruction?

500 cycles
100 cycles
104 cycles (Speedup ratio ~4.8x)
200 cycles

Explanation: Pipelined time for n=100 instructions with k=5 stages = k + (n - 1) = 5 + 99 = 104 cycles. Non-pipelined time = 100 * 5 = 500 cycles. Speedup ratio = 500 / 104 ≈ 4.807x. 📖 Full Topic Concept & Cheat Sheet: http://localhost:3000/topics/computer-architecture

Question 2: [CoA Quiz Q2/10] Which cache mapping technique allows a block from main memory to be placed in ANY cache line location?

Fully Associative Mapping
Direct Mapping
2-Way Set Associative Mapping
4-Way Set Associative Mapping

Explanation: Fully Associative mapping allows any memory block to reside in any cache line, offering highest hit ratios but requiring expensive content-addressable memory (CAM) comparison. 📖 Full Topic Concept & Cheat Sheet: http://localhost:3000/topics/computer-architecture

Question 3: [CoA Quiz Q3/10] What type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that is still in the pipeline?

Structural Hazard (Resource Conflict)
Data Hazard (RAW - Read After Write)
Control Hazard (Branch Penalty)
Memory Cache Hazard

Explanation: Data Hazards occur when instruction data dependencies exist (e.g. RAW hazard). Solved using Operand Forwarding or Pipeline Stalls (Bubbles). 📖 Full Topic Concept & Cheat Sheet: http://localhost:3000/topics/computer-architecture

Question 4: [CoA Quiz Q4/10] In Write-Through vs Write-Back cache memory policy, which statement is true?

Write-Back updates Main Memory on every single write operation
Write-Through requires dirty bits for every cache line
Write-Back never writes data to Main Memory
Write-Through updates both Cache and Main Memory simultaneously

Explanation: Write-Through updates main memory immediately upon every cache write. Write-Back updates main memory only when a modified (dirty) block is evicted. 📖 Full Topic Concept & Cheat Sheet: http://localhost:3000/topics/computer-architecture

Question 5: [CoA Quiz Q5/10] RISC (Reduced Instruction Set Computer) architectures are characterized by which design philosophy?

Microprogrammed control unit and variable length instructions
Complex memory-to-memory operations in single instruction
Hardwired control unit, fixed length instructions, and Load-Store architecture
Large variable instruction set with multiple addressing modes

Explanation: RISC uses hardwired control, single-cycle instruction execution, fixed-length 32-bit instructions, and Load-Store architecture where only Load/Store access memory. 📖 Full Topic Concept & Cheat Sheet: http://localhost:3000/topics/computer-architecture

Concept Breakdown

Detailed technical explanation

Computer Architecture Core Concept Breakdown

Instruction Pipelining: Pipelining increases CPU instruction throughput by overlapping instruction execution stages (Fetch, Decode, Execute, Memory, Writeback).
- Non-Pipelined Time: T_n = n * k * \tau
- Pipelined Time: T_p = (k + n - 1) * \tau
- Ideal Speedup (S): S_k = (n * k) / (k + n - 1) -> k as n -> infinity
Cache Memory & Address Structure:
- Direct Mapping Address: | Tag | Line / Index | Word / Offset |
- Set Associative Address: | Tag | Set Index | Word / Offset |
- Fully Associative Address: | Tag | Word / Offset |
Cache Replacement Policies & Write Policies:
- Write-Through: Every write operation updates both cache and main memory.
- Write-Back: Writes occur only in cache; main memory is updated when a dirty block is evicted.

Key Revision Rules

Essential formulas and core points to memorize

1Pipelined Time Formula: Execution time for n instructions on a k-stage pipeline is T = (k + n - 1) * ClockCycleTime.
2Pipelining Speedup Ratio: S = (n * k) / (k + n - 1). As n -> ∞, Speedup approaches k (the number of stages).
3Cache Memory Placement: Direct Mapping (1 slot per block), Set Associative (N slots per set), Fully Associative (Any slot).
4Pipeline Hazards: Structural (Hardware collision), Data (RAW/WAR/WAW dependencies), Control (Branch instructions).
5RISC vs CISC: RISC relies on Hardwired Control and Load-Store architecture; CISC relies on Microprogrammed Control and variable instruction formats.

Common Exam Mistakes

Where students frequently lose marks

Confusing Pipelined execution time formula for 1 instruction vs n instructions: For 1 instruction it takes k cycles; for n instructions it takes k + n - 1 cycles.

Confusing Write-Through (updates main memory immediately) with Write-Back (uses dirty bit, updates memory on eviction).

Assuming RISC has microprogrammed control: RISC uses hardwired control for single-cycle execution.

Topic Quiz Practice

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Question 1

[CoA Quiz Q1/10] In a 5-stage instruction pipeline, executing 100 instructions without hazards takes how many clock cycles assuming non-pipelined execution takes 5 cycles per instruction?

Master Computer Architecture