Register Transfer & Microoperations
Subject: Computer Architecture and Organization
CPU Registers (PC, MAR, MDR, IR, Accumulator), Register Transfer Language (RTL), Bus transfers, and Microoperations.
Concept Summary
Key Revision Rules & Formulas
- Program Counter (PC) holds the address of the next instruction to fetch.
- Memory Address Register (MAR) holds the memory address being read or written.
- Memory Data Register (MDR/MBR) holds the data fetched from or written to memory.
- Instruction Register (IR) holds the opcode of the currently executing instruction.
- Microoperations are elementary operations performed on data stored in registers (Arithmetic, Logic, Shift).
Common Exam Pitfalls
- Confusing PC (holds address of NEXT instruction) with IR (holds CURRENT instruction opcode).
- Assuming register transfer takes multiple cycles; elementary microoperations execute in a single clock pulse.
Sample Practice Questions
Question 1: कौन सा उपकरण डाटा व प्रोग्राम के मध्य अन्तर करता है -
- इनपुट उपकरण
- आउटपुट उपकरण
- स्मृति उपकरण
- प्रोसेसर उपकरण
Explanation: प्रोसेसर (CPU) डेटा और प्रोग्राम निर्देशों को अलग करता है और उन्हें प्रोसेस करता है।
Question 2: सीपीयू रजिस्टर के आकार (साइज़) को ______ भी कहा जाता है, और यह किसी भी दिए गए समय पर डेटा की मात्रा को इंगित करता है, जिसके साथ कंप्यूटर कार्य करता है।
- शब्द का आकार (Word size)
- कैश मेमोरी का आकार (Cache memory size)
- सिस्टम बस का आकार (System bus size)
- भण्डारण क्षमता (Storage capacity)
Explanation:
Question 3: निम्न में से कौन सा रजिस्टर सेकेंडरी स्टोरेज के साथ इंटरैक्ट कर सकता है -
- PC
- MAR
- MDR
- IR
Explanation:
Question 4: ______, एक सीपीयू (CPU) रजिस्टर है, जिसका उपयोग प्रोग्राम निष्पादन के दौरान अगले निर्देश (इंस्ट्रक्शन) के एड्रेस को संग्रहित (स्टोर) करने के लिए किया जाता है।
- एक्यूमुलेटर (Accumulator)
- इंडेक्स रजिस्टर (Index register)
- प्रोग्राम काउन्टर (Program counter)
- मेमोरी डेटा रजिस्टर (Memory data register)
Explanation:
Question 5: What does the notation R2 ← R1 signify in Register Transfer Language (RTL)?
- The contents of register R2 are copied into register R1
- The contents of register R1 are copied into register R2
- Registers R1 and R2 swap their stored contents
- Register R1 is incremented by the value of R2
Explanation: In Register Transfer Language, R2 ← R1 indicates a transfer of information from source register R1 to destination register R2. The contents of R1 remain unchanged.
Question 6: Which CPU register stores the address of the memory location currently being accessed for a Read or Write operation?
- Program Counter (PC)
- Memory Data Register (MDR)
- Memory Address Register (MAR)
- Instruction Register (IR)
Explanation: The Memory Address Register (MAR) holds the memory address that the CPU wants to read from or write to over the address bus.
Question 7: What is the function of the Accumulator (AC) register in a basic CPU architecture?
- Stores the opcode of the next instruction to be fetched
- Holds one of the operands and the intermediate result of ALU operations
- Maintains the count of instructions executed per second
- Stores external interrupt vector addresses
Explanation: The Accumulator (AC) is a general-purpose processor register that holds initial operational operands and receives the computed outputs from the ALU.
Question 8: Which microoperation shifts a binary number to the left by 1 bit, filling the vacant low-order bit position with 0?
- Arithmetic Right Shift
- Logical Left Shift
- Circular Right Shift (Rotate)
- Arithmetic Right Shift with Sign Extension
Explanation: Logical Left Shift (shl) shifts all bits one position to the left. The vacant LSB is filled with 0, effectively multiplying unsigned numbers by 2.
Question 9: What condition causes an Arithmetic Shift Left overflow during binary 2's complement shifting?
- When the Most Significant Bit (MSB) changes state during or after the shift operation
- When the Least Significant Bit (LSB) becomes 1
- When the Carry flag is reset to 0
- When the sign bit matches the parity bit
Explanation: Arithmetic Shift Left can cause overflow if the MSB (sign bit) changes during the shift, indicating the multiplied result exceeded register capacity.
Question 10: In a common bus system constructed using multiplexers for 8 registers of 16 bits each, how many selection lines are required for the multiplexers?
- 2 selection lines
- 3 selection lines
- 4 selection lines
- 8 selection lines
Explanation: To select 1 out of 8 registers, 2^n >= 8 => n = 3 selection lines (S2, S1, S0) are required for each MUX.