What condition causes an Arithmetic Shift Left overflow during binary 2's complement shifting?

Subject: Computer Architecture and Organization

Topic: Register Transfer & Microoperations

Options:

1. Option A: When the Most Significant Bit (MSB) changes state during or after the shift operation
2. Option B: When the Least Significant Bit (LSB) becomes 1
3. Option C: When the Carry flag is reset to 0
4. Option D: When the sign bit matches the parity bit

Correct Answer:

Option A: When the Most Significant Bit (MSB) changes state during or after the shift operation

Explanation:

Arithmetic Shift Left can cause overflow if the MSB (sign bit) changes during the shift, indicating the multiplied result exceeded register capacity.