Instruction Set Architecture & Addressing Modes
Subject: Computer Architecture and Organization
Instruction formats, Opcode & Operands, Addressing modes (Direct, Indirect, Register, Immediate, Relative, Indexed), RISC vs CISC.
Concept Summary
Key Revision Rules & Formulas
- Direct Addressing Mode: Instruction contains the effective address of the operand directly.
- Indirect Addressing Mode: Instruction contains a pointer address that points to the effective address (requires 2 memory references).
- Immediate Addressing Mode: Operand value is directly specified within the instruction opcode field.
- RISC (Reduced Instruction Set Computer) emphasizes single-cycle execution and fixed-length instructions; CISC emphasizes complex multi-cycle variable-length instructions.
Common Exam Pitfalls
- Counting 1 memory reference for Indirect Addressing instead of 2 (one for pointer, one for data).
- Assuming Immediate Addressing requires memory access for operands (the operand is inside the instruction itself).
Sample Practice Questions
Question 1: CISC का मतलब है -
- Complex Instruction Set Computer
- Complete Instruction Sequential Compilation
- Complex Instruction Sequential Compiler
- None of the above
Explanation:
Question 2: निम्नलिखित में से कौन सी यूनिट किसी प्रोग्राम के निर्देशों को कैसे पूरा करने के लिए कंप्यूटर के अन्य घटकों को निर्देश देकर सिस्टम की अन्य सभी यूनिट्स की गतिविधियों का समन्वय करती है?
- कंट्रोल यूनिट
- अरिथमेटिक एंड लॉजिक यूनिट
- स्टोरेज यूनिट
- आउटपुट यूनिट
Explanation:
Question 3: Which addressing mode calculates the effective address of the operand as: Effective Address = (Contents of Register) + Address Field Value?
- Direct Addressing Mode
- Indexed Addressing Mode / Base Register Addressing
- Immediate Addressing Mode
- Implied Addressing Mode
Explanation: In Indexed / Base Register Addressing Mode, the effective address is computed dynamically by adding the constant value in the instruction address field to the contents of an index or base register (EA = R + X).
Question 4: An instruction of the form 'ADD R1, R2, R3' belongs to which type of instruction architecture format?
- 0-Address Instruction
- 1-Address Instruction
- 2-Address Instruction
- 3-Address Instruction
Explanation: A 3-address instruction explicitly specifies two source operands and one destination operand (e.g., R1 = R2 + R3), minimizing memory traffic at the cost of longer instruction bit-lengths.
Question 5: Which of the following is a fundamental characteristic feature of RISC (Reduced Instruction Set Computer) processors?
- Variable length instructions with complex microcode
- Fixed length instructions with Load/Store architecture and register-to-register operations
- Multiple memory access instructions per arithmetic operation
- Large number of addressing modes with microprogrammed control
Explanation: RISC processors feature fixed-length instruction encoding, hardwired control logic, a large register file, and strict Load/Store architecture (memory is accessed only via LOAD and STORE instructions).
Question 6: In which addressing mode is the operand value explicitly contained within the instruction itself?
- Direct Addressing Mode
- Immediate Addressing Mode
- Register Indirect Addressing Mode
- Relative Addressing Mode
Explanation: In Immediate Addressing Mode, the operand value is part of the instruction opcode field, requiring zero additional memory fetches for operand data.
Question 7: How many memory references are required to fetch the operand in Indirect Addressing Mode?
- 0 memory references
- 1 memory reference
- 2 memory references
- 3 memory references
Explanation: Indirect Addressing requires 2 memory access cycles: 1st cycle fetches the pointer address from memory, and 2nd cycle fetches the actual operand data from that address.
Question 8: Which instruction format relies on a Stack data structure for zero-address operand operations?
- 0-Address Instruction Format
- 1-Address Instruction Format (Accumulator based)
- 2-Address Instruction Format
- 3-Address Instruction Format
Explanation: 0-address instructions (such as PUSH, POP, ADD) operate implicitly on top of a Evaluation Stack without specifying explicit memory or register address fields.
Question 9: In PC-Relative Addressing Mode, how is the effective address (EA) calculated for branch instructions?
- EA = Contents of Accumulator + Opcode Field
- EA = Contents of Program Counter (PC) + Address Offset Field
- EA = Memory Address Register + Base Register
- EA = Stack Pointer - Index Register
Explanation: PC-Relative addressing calculates Effective Address by adding the signed displacement offset in the instruction to the updated Program Counter value (EA = PC + Offset).
Question 10: What characterizes CISC (Complex Instruction Set Computer) processors compared to RISC?
- Fixed instruction length with simple hardwired control logic
- Variable instruction length, microprogrammed control, and rich addressing modes
- Only LOAD and STORE instructions access memory
- Large uniform register file with 1 instruction per cycle execution
Explanation: CISC processors (like x86) feature variable length instruction encodings, complex microprogrammed control units, and extensive addressing modes permitting direct memory operands.