Concept Summary

Key Revision Rules & Formulas

• 🚀 Pipelining Speedup & Execution Time: For n instructions in a k-stage pipeline with clock cycle t_clk, Total Time = [k + (n - 1)] * t_clk. Ideal Speedup S = k (for infinite instructions n -> infinity). Actual Speedup S = (n * k) / [k + (n - 1)].
• ⏱️ Clock Cycle Time Formula: t_clk = max(stage delays) + t_r, where t_r is the pipeline register delay.
• ⚠️ Pipeline Hazards Overview: 1) Structural Hazards (Resource conflicts, e.g., single memory port for Instruction & Data), 2) Data Hazards (RAW/Read-After-Write, WAR/Write-After-Read, WAW/Write-After-Write), 3) Control Hazards (Branching, Jumps, Calls).
• ⚡ Data Forwarding (Bypassing): Resolves ALU-to-ALU RAW data hazards with 0 stalls by routing computed values from EX/MEM or MEM/WB pipeline registers directly to ALU inputs in subsequent cycles.
• ⏳ Load-Use Data Hazard: A Load instruction (LW) followed immediately by a dependent instruction requires 1 STALL CYCLE (bubble) even with forwarding, because loaded data is available only at the end of MEM stage (Stage 4).
• 🎯 Branch Penalty & Control Hazards: Resolving branch target at EX stage (Stage 3) incurs a 2-cycle penalty for taken branches if no branch prediction is used. Advanced techniques: Branch Prediction (Static/Dynamic), Delayed Branching.
• 💻 Flynn's Taxonomy Classification: 1) SISD (Traditional single CPU), 2) SIMD (GPUs, Vector processors, Array processors - single instruction stream on multiple data streams), 3) MISD (Redundant fault-tolerant systems, Systolic arrays - multiple instructions on single data stream), 4) MIMD (Multicore CPUs, Clusters, Multiprocessors).
• 📈 Amdahl's Law (Speedup Limit): Speedup S(N) = 1 / [(1 - f) + (f / N)], where f is the parallel fraction and (1 - f) is the sequential fraction. Maximum theoretical speedup limit as N -> infinity is S_max = 1 / (1 - f).
• 🧠 UMA vs. NUMA Memory Architectures: Uniform Memory Access (UMA / SMP) provides equal access latency to main memory for all CPUs via shared bus. Non-Uniform Memory Access (NUMA) distributes physical RAM across processor nodes, making local memory access faster than remote memory access.
• 🔀 Hardware Multithreading (SMT vs. Fine-Grained): Simultaneous Multithreading (SMT / Hyper-Threading) allows wide superscalar issue logic to issue instructions from MULTIPLE independent threads in the EXACT SAME clock cycle.

Common Exam Pitfalls

• Mistake: Calculating ideal speedup ratio as k for infinite instructions, but forgetting that for finite n instructions, Speedup = (n * k) / [k + (n - 1)].
• Mistake: Assuming Data Forwarding eliminates ALL data hazards. A Load-Use hazard (LW followed by ADD) strictly requires 1 stall cycle even with full forwarding.
• Mistake: Confusing SIMD (Vector / GPU array processing) with MIMD (Multi-core independent threading).
• Mistake: Forgetting to add register delay (t_r) when calculating pipeline clock cycle time t_clk = max(stage_delays) + t_r.
• Mistake: Assuming Amdahl's Law allows infinite speedup when core count N -> infinity (Speedup is hard-capped at 1 / (1 - f) by the sequential portion).

Sample Practice Questions