Input-Output (I/O) Organization & DMA
Subject: Computer Architecture and Organization
Data transfer modes: Programmed I/O, Interrupt-Driven I/O, Direct Memory Access (DMA), Priority Interrupts, Daisy Chaining.
Concept Summary
Key Revision Rules & Formulas
- Programmed I/O: CPU continuously polls I/O status flags (busy waiting, highly inefficient).
- Interrupt-Driven I/O: I/O module interrupts CPU when ready, freeing CPU to execute other tasks.
- Direct Memory Access (DMA): DMA controller handles high-speed bulk data transfers directly between I/O devices and RAM without CPU intervention.
- Bus Stealing / Cycle Stealing: DMA controller temporarily suspends CPU bus access for 1 bus cycle to transfer 1 word.
Common Exam Pitfalls
- Assuming CPU is involved during DMA word transfer (DMA transfers directly to/from RAM, CPU only initializes DMA registers).
- Confusing Burst Mode DMA (transfers entire block at once) with Cycle Stealing DMA (transfers 1 word per stolen bus cycle).
Sample Practice Questions
Question 1: ......... पोर्ट को काॅम पोर्ट के नाम से भी जाना जाता है-
- आर. जे-45
- सीरियल
- पैरेलल
- आर. जे-11
Explanation: सीरियल पोर्ट को COM (Communication) पोर्ट कहा जाता है, जो डेटा को क्रमिक रूप से ट्रांसफर करता है। इसे कभी-कभी COM पोर्ट या RS-232 पोर्ट कहा जाता है, जो इसका तकनीकी नाम है।
Question 2: कम समय में किसी को तथा कहीं (to and form) से बड़ी मात्रा में स्थानान्तरित करने के लिए कौनसी तकनीक अधिक पंसद की जाती है -
- DMA
- Interrupt driven I/O
- Programmed I/O
- इनमें से कोई नहीं
Explanation: DMA का पूर्ण रूप Direct Memory Access होता है। यह Computer bus architecture द्वारा provide करवाई जा रही विशेष capability होती है जो डाटा को एक डिस्क ड्राइव जैसे attached device directly computer motherboard memory पर भेजता है।
Question 3: I/O सिस्टम का संचार अनुक्रम है –
- डिवाइस कंट्रोलर ↔ डिवाइस ड्राइवर ↔ I/O डिवाइसेज़ ↔ OS
- I/0 डिवाइसेज़ ↔ OS ↔ डिवाइस ड्राइवर ↔ डिवाइस कंट्रोलर
- OS ↔ डिवाइस कंट्रोलर ↔ डिवाइस ड्राइवर ↔ I/O डिवाइसेज़
- OS ↔ डिवाइस ड्राइवर ↔ डिवाइस कंट्रोलर ↔ I/O डिवाइसेज़
Explanation:
Question 4: In Direct Memory Access (DMA) data transfer, what happens during 'Cycle Stealing' mode?
- DMA controller takes control of the system bus for the entire block transfer duration
- DMA controller steals one bus cycle from the CPU to transfer a single word of data
- CPU halts permanently until peripheral power is disconnected
- I/O device bypasses main RAM memory and writes directly into CPU instruction registers
Explanation: In Cycle Stealing mode, the DMA controller requests control of the system bus from the CPU for just one clock cycle to transfer a single data word, after which control is immediately yielded back to the CPU.
Question 5: Which interrupt priority scheme connects multiple I/O devices in a hardware series chain where the device nearest to the CPU has the highest priority?
- Parallel Priority Interrupt
- Daisy Chaining Scheme
- Polling Interrupt Method
- Software Vectored Interrupt
Explanation: Daisy Chaining is a hardware priority scheme where all devices are connected serially along an Interrupt Acknowledge line. The device closest to the CPU intercepts the signal first, giving it the highest priority.
Question 6: What is the primary drawback of Programmed I/O data transfer mode?
- CPU wastes significant processing cycles constantly polling I/O status flags in a busy-wait loop
- Requires high cost DMA controllers
- Only works with optical storage
- Causes hard drive corruptions
Explanation: In Programmed I/O, the CPU remains trapped in a tight status-check loop (busy waiting) until the peripheral is ready, wasting CPU processing bandwidth.
Question 7: Which bus signal line is asserted by a DMA controller to request control of system buses from the CPU?
- Bus Request (HOLD / BR)
- Interrupt Request (IRQ)
- Memory Read (MEMR)
- Address Enable (AEN)
Explanation: The DMA controller asserts the HOLD / Bus Request (BR) line to inform the CPU that it needs master control of system address and data buses.
Question 8: What CPU response signal confirms that CPU has yielded control of system buses to DMA controller?
- Bus Grant / HOLD Acknowledge (HLDA)
- Interrupt Acknowledge (INTA)
- Ready Line
- Chip Select (CS)
Explanation: The CPU places its output drivers in High-Impedance (Hi-Z) state and asserts HLDA (HOLD Acknowledge) to grant bus mastership to the DMA controller.
Question 9: In Interrupt-Initiated I/O, how does the CPU know which device requested an interrupt in Vectored Interrupt mode?
- The interrupting device supplies an interrupt vector number/address over the data bus during INTA cycle
- CPU polls every device one by one in software loop
- CPU reads the hard drive partition table
- Device lights an LED indicator on motherboard
Explanation: In Vectored Interrupts, the device places its unique vector identifier/address on the data bus when it receives INTA (Interrupt Acknowledge) from CPU.
Question 10: What is Memory-Mapped I/O compared to Isolated (I/O-Mapped) I/O?
- I/O device registers are assigned addresses within the same memory address space as RAM
- I/O devices use a separate 16-bit address space with special IN and OUT instructions
- I/O data is stored on optical discs
- I/O devices do not require address lines
Explanation: In Memory-Mapped I/O, peripheral registers share the unified memory address space, allowing normal memory instructions (MOV, ADD) to access I/O ports.