Which bus signal line is asserted by a DMA controller to request control of system buses from the CPU?

Subject: Computer Architecture and Organization

Topic: Input-Output (I/O) Organization & DMA

Options:

1. Option A: Bus Request (HOLD / BR)
2. Option B: Interrupt Request (IRQ)
3. Option C: Memory Read (MEMR)
4. Option D: Address Enable (AEN)

Correct Answer:

Option A: Bus Request (HOLD / BR)

Explanation:

The DMA controller asserts the HOLD / Bus Request (BR) line to inform the CPU that it needs master control of system address and data buses.