Subject Syllabus Hub294+ MCQs6 Topics

Digital Logic Systems

Number representations, Boolean algebra, logic minimization (K-maps), combinational circuit design, flip-flops, counters, and sequential circuits.

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Topic 15 Key Rules

Digital Logic Systems

This subject covers the fundamental principles of digital hardware design, ranging from basic number representation and logic gates to complex combinational and sequential circuit blocks like adders, registers, counters, and finite state machines.

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Topic 25 Key Rules

Digital Logic Systems Unit 1: Fundamental Concepts

# Unit 1: Fundamental Concepts This unit covers the foundational building blocks of digital systems: number systems, data representation, binary arithmetic, binary codes, basic logic gates, and the postulates/theorems of Boolean algebra. --- ## 1. Number Systems and Base Conversions Digital systems process binary data ($0$ and $1$). However, humans use decimal, and programmers often use octal or hexadecimal for brevity. A number system with base (or radix) $r$ uses $r$ unique symbols. | Number System | Radix ($r$) | Allowed Digits / Symbols | Example | | :--- | :--- | :--- | :--- | | **Binary** | $2$ | $0, 1$ | $1011.01_2$ | | **Octal** | $8$ | $0, 1, 2, 3, 4, 5, 6, 7$ | $74.5_8$ | | **Decimal** | $10$ | $0, 1, 2, 3, 4, 5, 6, 7, 8, 9$ | $98.6_{10}$ | | **Hexadecimal** | $16$ | $0\text{-}9$, $\text{A}(10), \text{B}(11), \text{C}(12), \text{D}(13), \text{E}(14), \text{F}(15)$ | $3\text{A}.\text{C}_{16}$ | ### 1.1 Base Conversions 1. **Any Base to Decimal**: Sum the digits multiplied by their positional weight $r^i$. $$\text{Value} = \sum_{i=-m}^{n-1} d_i \cdot r^i$$ *Example:* $101.11_2 = (1 \cdot 2^2) + (0 \cdot 2^1) + (1 \cdot 2^0) + (1 \cdot 2^{-1}) + (1 \cdot 2^{-2}) = 4 + 0 + 1 + 0.5 + 0.25 = 5.75_{10}$. 2. **Decimal to Any Base**: - **Integer part**: Successive division by target base $r$, collecting remainders from bottom to top (LSB to MSB). - **Fractional part**: Successive multiplication by target base $r$, collecting integer carries from top to bottom. 3. **Binary $\leftrightarrow$ Octal / Hexadecimal**: Group binary bits in sets of $3$ (for octal) or $4$ (for hex) starting from the radix point, moving left for integers and right for fractions. Pad with zeros if necessary. --- ## 2. Signed Number Representations In digital hardware, negative numbers are represented using binary signs. There are three primary formats for representing signed integers using $n$ bits: ### 2.1 Sign and Magnitude (SM) - **MSB (Most Significant Bit)**: $0$ for positive ($+$), $1$ for negative ($-$). - **Remaining $n-1$ bits**: Represent the absolute magnitude of the number. - **Range**: $-(2^{n-1} - 1)$ to $+(2^{n-1} - 1)$. - **Pitfall**: Dual representation of zero ($+0 = 000...0$, $-0 = 100...0$), which complicates ALU design. ### 2.2 1's Complement Notation - **Positive Numbers**: Same as sign-magnitude with MSB = $0$. - **Negative Numbers**: Obtained by bitwise inverting (NOT operation) all bits of the positive counterpart. - **Range**: $-(2^{n-1} - 1)$ to $+(2^{n-1} - 1)$. - **Pitfall**: Still has dual representation of zero ($+0 = 000...0$, $-0 = 111...1$). ### 2.3 2's Complement Notation (Standard in Modern ALUs) - **Positive Numbers**: Same as sign-magnitude with MSB = $0$. - **Negative Numbers**: Obtained by adding $1$ to the 1's complement of the number: $$\text{2's Complement} = \text{1's Complement} + 1$$ - **Range**: $-2^{n-1}$ to $+(2^{n-1} - 1)$. - **Advantages**: - Unique representation of zero ($000...0$). - Simple subtraction: $A - B$ is computed as $A + (-B)$ using the same adder hardware. | Decimal (for $n=4$) | Sign-Magnitude | 1's Complement | 2's Complement | | :--- | :--- | :--- | :--- | | $+7$ | $0111$ | $0111$ | $0111$ | | $+0$ | $0000$ | $0000$ | $0000$ | | $-0$ | $1000$ | $1111$ | N/A | | $-7$ | $1111$ | $1000$ | $1001$ | | $-8$ | N/A | N/A | $1000$ | --- ## 3. Fixed-Point vs. Floating-Point Representation - **Fixed-Point**: The position of the binary point is pre-determined (usually at the end for integers, or after the MSB for fractions). - Simple hardware, limited range, fixed precision. - **Floating-Point**: Represents numbers as $\pm M \times r^E$, where $M$ is the mantissa, $r$ is the base, and $E$ is the exponent. Standardized by IEEE 754 (Single Precision: 32-bit, Double Precision: 64-bit). - High dynamic range, complex hardware, variable precision. --- ## 4. Binary Codes ### 4.1 Classification of Codes 1. **Weighted Codes**: Each bit position has a specific weight. - *Examples*: BCD (8421), 2421, 84-2-1. 2. **Non-Weighted Codes**: Position has no arithmetic weight. - *Examples*: Excess-3, Gray Code. 3. **Self-Complementing Codes**: A code where the 1's complement of a codeword represents the 9's complement of its decimal digit. - *Examples*: Excess-3, 2421. (Note: 8421 BCD is **not** self-complementing). 4. **Reflected/Unit-Distance Codes**: Only one bit changes between consecutive numbers. - *Example*: Gray Code. Essential for reducing glitches in mechanical shafts and asynchronous transitions. ### 4.2 Gray Code Conversions - **Binary to Gray**: - $G_{n-1} = B_{n-1}$ (Keep MSB) - $G_i = B_{i+1} \oplus B_i$ for $i < n-1$ - **Gray to Binary**: - $B_{n-1} = G_{n-1}$ (Keep MSB) - $B_i = B_{i+1} \oplus G_i$ for $i < n-1$ ### 4.3 BCD Addition Rule If the sum of two BCD digits is greater than $9$ ($1001_2$) or if a carry is generated from the digit position: - Add $6$ ($0110_2$) to that digit group to skip the 6 invalid states ($1010$ to $1111$), and propagate the carry to the next higher digit. --- ## 5. Basic Logic Gates Logic gates are physical electronic devices implementing Boolean functions. ``` AND OR NOT +-----+ +-----+ +---+ A ---| \ A ---\ \ | | | & )--- Y | \ )--- Y A -----| >o|--- Y B ---| / B ---/ / | | +-----+ +-----+ +---+ Y = A • B Y = A + B Y = A' NAND NOR XOR +-----+o +-----+o +---+ A ---| \ A ---\ \ A | \ \ | & )--- Y | \ )--- Y | | )--- Y B ---| / B ---/ / B | / / +-----+o +-----+o +---+ Y = (A • B)' Y = (A + B)' Y = A ⊕ B = AB'+A'B ``` ### 5.1 Universal Gates **NAND** and **NOR** are universal gates because any Boolean expression can be realized using only NAND or only NOR gates. - *Minimum gates for standard functions*: | Target Function | NAND Gate Count | NOR Gate Count | | :--- | :---: | :---: | | **NOT** | $1$ | $1$ | | **AND** | $2$ | $3$ | | **OR** | $3$ | $2$ | | **XOR** | $4$ | $5$ | | **XNOR** | $5$ | $4$ | --- ## 6. Boolean Algebra: Postulates & Theorems Boolean algebra operates on a set $\{0, 1\}$ with operators $+$ (OR), $\cdot$ (AND), and $'$ (NOT). ### 6.1 Huntington's Postulates 1. **Closure**: For any $a, b \in B$, $a+b \in B$ and $a \cdot b \in B$. 2. **Identity**: $a + 0 = a$ and $a \cdot 1 = a$. 3. **Commutative**: $a + b = b + a$ and $a \cdot b = b \cdot a$. 4. **Distributive**: - $a \cdot (b + c) = (a \cdot b) + (a \cdot c)$ - $a + (b \cdot c) = (a + b) \cdot (a + c)$ *(Highly tested in exams)* 5. **Complement**: $a + a' = 1$ and $a \cdot a' = 0$. ### 6.2 Key Theorems of Boolean Algebra * **Idempotent Law**: $A + A = A$, $A \cdot A = A$. * **Boundedness (Dominance)**: $A + 1 = 1$, $A \cdot 0 = 0$. * **Involution Law**: $(A')' = A$. * **Absorption Law**: - $A + AB = A$ - $A(A + B) = A$ - $A + A'B = A + B$ *(Simplification powerhouse!)* * **Demorgan's Laws**: - $(A + B)' = A' \cdot B'$ (The complement of a sum is the product of complements) - $(A \cdot B)' = A' + B'$ (The complement of a product is the sum of complements) * **Consensus Theorem**: - $AB + A'C + BC = AB + A'C$ - $(A+B)(A'+C)(B+C) = (A+B)(A'+C)$ - *Proof*: $BC = BC(A+A') = ABC + A'BC$. Substitute this back: $AB + A'C + ABC + A'BC = AB(1+C) + A'C(1+B) = AB + A'C$. * **Shannon's Expansion Theorem**: - $F(A, B, C, ...) = A \cdot F(1, B, C, ...) + A' \cdot F(0, B, C, ...)$ --- ## 7. Exam Tips & Common Pitfalls > [!WARNING] > - **Overflow in 2's Complement**: Arithmetic overflow occurs only when adding two numbers of the same sign and getting a result with the opposite sign. Formally: $V = C_{in} \oplus C_{out}$ at the MSB adder stage. If $V=1$, overflow occurred. > - **Distributive Law Trap**: Students often forget that OR distributes over AND: $A + BC = (A+B)(A+C)$. > - **Consensus Theorem Identification**: Look for three terms, where each of three variables ($A, B, C$) appears twice, and one variable appears in both complemented and uncomplemented forms. The term containing only uncomplemented/complemented counterparts of the other two variables is redundant.

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Topic 36 Key Rules

Digital Logic Systems Unit 2: Minimization Techniques

# Unit 2: Minimization Techniques and Logic Gates Boolean expression minimization is crucial for reducing the hardware complexity (number of gates and inputs) required to implement a logic circuit. This unit covers the Principle of Duality, Canonical/Standard Forms, Karnaugh Maps, and the Quine-McCluskey tabulation method. --- ## 1. Principle of Duality The **Principle of Duality** states that any algebraic identity in Boolean algebra remains valid if all operators and identity elements are interchanged: * Replace AND ($\cdot$) with OR ($+$). * Replace OR ($+$) with AND ($\cdot$). * Replace $1$ with $0$, and $0$ with $1$. * **Keep variables unchanged** (do NOT invert them). *Example:* - **Original Identity**: $A + A'B = A + B$ - **Dual Identity**: $A \cdot (A' + B) = A \cdot B$ ### 1.1 Dual vs. Complement - **Dual ($F^d$)**: Swap operators ($+ \leftrightarrow \cdot$) and constants ($0 \leftrightarrow 1$). Keep variables $x_i$ as $x_i$. - **Complement ($F'$)**: Swap operators ($+ \leftrightarrow \cdot$) and constants ($0 \leftrightarrow 1$), **and invert all variables** ($x_i \leftrightarrow x_i'$). $$F'(x_1, x_2, ..., x_n, +, \cdot, 0, 1) = F^d(x_1', x_2', ..., x_n', \cdot, +, 1, 0)$$ --- ## 2. Canonical and Standard Forms ### 2.1 Minterms ($m$) and Maxterms ($M$) For $n$ Boolean variables, there are $2^n$ unique product combinations (minterms) and $2^n$ unique sum combinations (maxterms). * **Minterm ($m_i$)**: A product (AND) of all $n$ variables, where a variable is in uncomplemented form if its binary value is $1$, and in complemented form if it is $0$. Minterm evaluates to $1$ for exactly one input combination. * **Maxterm ($M_i$)**: A sum (OR) of all $n$ variables, where a variable is in uncomplemented form if its binary value is $0$, and in complemented form if it is $1$. Maxterm evaluates to $0$ for exactly one input combination. $$\text{Relationship: } M_i = (m_i)'$$ *Example for 3 variables ($A, B, C$):* - Row $3$ (binary $011$): - Minterm $m_3 = A'BC$ - Maxterm $M_3 = A + B' + C'$ ### 2.2 Sum of Products (SOP) vs. Product of Sums (POS) 1. **Sum of Products (SOP)**: Terms are ANDed together, and then these product terms are ORed. Represents the active-high ($1$) outputs of a truth table. * *Canonical SOP (Standard SOP)*: Every product term contains all variables. *Example:* $F(A,B,C) = \sum m(1, 4, 7) = A'B'C + AB'C' + ABC$. 2. **Product of Sums (POS)**: Terms are ORed together, and then these sum terms are ANDed. Represents the active-low ($0$) outputs of a truth table. * *Canonical POS (Standard POS)*: Every sum term contains all variables. *Example:* $F(A,B,C) = \prod M(0, 2, 3, 5, 6) = (A+B+C)(A+B'+C)(A+B'+C')(A'+B+C')(A'+B'+C)$. --- ## 3. Karnaugh Map (K-Map) Minimization A K-Map is a visual representation of a truth table. Cell addresses are arranged in **Gray Code** order (e.g., $00, 01, 11, 10$) so that adjacent cells differ by only one variable (unit distance). This allows minimization using the theorem $XY + XY' = X(Y+Y') = X$. ### 3.1 K-Map Structures #### 3-Variable K-Map (8 cells) ``` BC A \ 00 01 11 10 +----+----+----+----+ 0 | m0 | m1 | m3 | m2 | +----+----+----+----+ 1 | m4 | m5 | m7 | m6 | +----+----+----+----+ ``` #### 4-Variable K-Map (16 cells) ``` CD AB \ 00 01 11 10 +----+----+----+----+ 00 | m0 | m1 | m3 | m2 | +----+----+----+----+ 01 | m4 | m5 | m7 | m6 | +----+----+----+----+ 11 | m12| m13| m15| m14| +----+----+----+----+ 10 | m8 | m9 | m11| m10| +----+----+----+----+ ``` ### 3.2 Grouping Rules 1. **Pairs**: Group of $2$ adjacent cells (eliminates $1$ variable). 2. **Quads**: Group of $4$ adjacent cells (eliminates $2$ variables). 3. **Octets**: Group of $8$ adjacent cells (eliminates $3$ variables). 4. **Wrap-around**: Cells on the outer edges (left/right, top/bottom) are adjacent. 5. **Don't Care Conditions ($X$ or $d$)**: Used as $1$ if they help form a larger group (reducing terms); otherwise, they are treated as $0$ and ignored. ### 3.3 Definitions - **Implicant**: Any individual $1$ (or group of $1$s) on the K-Map. - **Prime Implicant (PI)**: A group of adjacent cells (size $2^k$) that cannot be combined into a larger group. - **Essential Prime Implicant (EPI)**: A Prime Implicant that contains at least one $1$ which is not covered by any other Prime Implicant. **Every EPI must be included in the final minimized expression.** --- ## 4. Quine-McCluskey (Tabulation) Method K-maps become unwieldy for $5$ or more variables. The **Quine-McCluskey (QM) method** is an algorithmic tabular approach that is easily programmed. ### 4.1 Step-by-Step Algorithm 1. **List Minterms**: Convert minterms to binary and group them by the number of $1$s they contain (Index groups). 2. **Compare and Combine**: Compare minterms of index group $G_i$ with $G_{i+1}$. If they differ by exactly one bit position, combine them, replace the differing bit with a dash ($-$), and place a checkmark ($\checkmark$) next to both source terms. 3. **Repeat**: Combine the new terms (comparing those with dashes in the same positions) until no further combinations are possible. Unchecked terms are **Prime Implicants (PI)**. 4. **EPI Selection**: Construct a Prime Implicant Chart. - Rows = PIs, Columns = Minterms. - Place an $X$ at the intersection of a row and column if the PI covers that minterm. - Identify columns with exactly one $X$. The PI corresponding to that row is an **Essential Prime Implicant (EPI)**. - Include EPIs in the final sum, remove covered minterms, and solve the remaining "simplified" chart (using Petrick's method if cyclic). ### 4.2 Tabulation Example Let $F(A,B,C,D) = \sum m(0, 1, 2, 8, 10, 11, 14, 15)$. **Step 1: Group by Number of 1's** * **Group 0 (0 ones)**: $m_0 \ (0000)$ * **Group 1 (1 ones)**: $m_1 \ (0001)$, $m_2 \ (0010)$, $m_8 \ (1000)$ * **Group 2 (2 ones)**: $m_{10} \ (1010)$ * **Group 3 (3 ones)**: $m_{11} \ (1011)$, $m_{14} \ (1110)$ * **Group 4 (4 ones)**: $m_{15} \ (1111)$ **Step 2: Combine Terms (1st Pass)** * $(0, 1) \rightarrow 000-$ * $(0, 2) \rightarrow 00-0$ * $(0, 8) \rightarrow -000$ * $(2, 10) \rightarrow -010$ * $(8, 10) \rightarrow 10-0$ * $(10, 11) \rightarrow 101-$ * $(10, 14) \rightarrow 1-10$ * $(11, 15) \rightarrow 1-11$ * $(14, 15) \rightarrow 111-$ **Step 3: Combine Terms (2nd Pass)** * $(0, 2, 8, 10) \rightarrow -0-0$ (Unchecked terms from first pass: $(0,1) \ (000-)$, $(10, 11) \ (101-)$, $(10, 14) \ (1-10)$, $(11, 15) \ (1-11)$, $(14, 15) \ (111-)$ cannot be matched further with identical dash structures). * Thus, PIs are: - $PI_1: -0-0 \rightarrow B'D'$ - $PI_2: 000- \rightarrow A'B'C'$ - $PI_3: 101- \rightarrow AB'C$ - $PI_4: 1-1- \rightarrow AC$ (obtained from combining $(10,11,14,15) \rightarrow 1-1-$) - $PI_5: 111- \rightarrow ABC$ *Solve the chart to select the minimum set covering all minterms.* --- ## 5. Exam Tips & Common Pitfalls > [!WARNING] > - **Redundant Groups in K-Map**: A group is redundant if all its cells are covered by other essential groups. Always identify EPIs first to avoid adding redundant terms. > - **Don't Care Trap**: You do not have to group all Don't Cares ($X$). Only group them if it expands the group size (e.g., converting a pair to a quad). > - **Gray Code Adjacency**: Remember that corners ($m_0, m_2, m_8, m_{10}$) are all adjacent in a 4-variable K-map and form a quad that simplifies to $B'D'$.

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Topic 46 Key Rules

Digital Logic Systems Unit 3: Gate Characteristics & Logic Families

# Unit 3: Digital Logic Gate Characteristics & Families Digital circuits are built using integrated circuits (ICs) classified into logic families based on their internal circuitry and device technology. This unit covers logic gate parameters, Transistor-Transistor Logic (TTL), Complementary Metal-Oxide-Semiconductor (CMOS) logic, and implementations using RTL, DTL, ECL, and MOS. --- ## 1. Digital Logic Gate Characteristics To compare different logic families, we evaluate specific electronic performance metrics: 1. **Propagation Delay ($t_{pd}$)**: The average time delay between input transition and output transition. Measured at $50\%$ voltage levels. - $t_{pHL}$: Delay from High to Low transition. - $t_{pLH}$: Delay from Low to High transition. - $t_{pd} = \frac{t_{pHL} + t_{pLH}}{2}$ 2. **Power Dissipation ($P_D$)**: The amount of power consumed by a gate. - Static Power: Consumed when state is idle. - Dynamic Power: Consumed during transitions (charging/discharging parasitic capacitances). 3. **Fan-Out**: The maximum number of inputs of the *same* logic family that a gate output can reliably drive without violating logic levels. - $\text{Fan-Out} = \min\left( \frac{I_{OH}}{I_{IH}}, \frac{I_{OL}}{I_{IL}} \right)$ 4. **Noise Margin ($NM$)**: The measure of a gate's noise immunity. - **High-Level Noise Margin**: $NM_H = V_{OH(min)} - V_{IH(min)}$ - **Low-Level Noise Margin**: $NM_L = V_{IL(max)} - V_{OL(max)}$ 5. **Figure of Merit (FOM)**: Product of speed and power: $$\text{FOM} = \text{Propagation Delay} \ (\text{ns}) \times \text{Power Dissipation} \ (\text{mW}) \quad [\text{unit: picoJoules, pJ}]$$ *A lower Figure of Merit represents a superior technology.* --- ## 2. Transistor-Transistor Logic (TTL) TTL is a bipolar logic family. The basic TTL gate is a **NAND gate**. ### 2.1 Operation of Totem-Pole TTL NAND Gate A standard TTL NAND gate consists of four stages: 1. **Input Stage (Multi-Emitter Transistor $Q_1$)**: Replaces input diodes of DTL. If any input $A$ or $B$ is Low ($0.2\text{V}$), $Q_1$'s base-emitter junction is forward-biased. $Q_1$ is saturated, pulling the base of Phase-Splitter $Q_2$ Low, turning it Off. 2. **Phase-Splitter Stage ($Q_2$)**: Splitting transistor. Since $Q_2$ is Off, no current flows to $Q_4$ (pull-down), so $Q_4$ is Off. The collector of $Q_2$ rises toward $V_{CC}$, turning $Q_3$ On. 3. **Active Pull-Up / Totem-Pole Output ($Q_3$, Diode $D_1$, $Q_4$)**: - **When Output is High**: $Q_3$ acts as an emitter follower, sourcing current to the load. Diode $D_1$ ensures $Q_3$ stays Off when output is Low. - **When Output is Low**: (Both inputs $A, B$ are High): $Q_1$ is reverse-active. Current flows into the base of $Q_2$, saturating it. $Q_2$ turns $Q_4$ On (saturating it to pull the output Low to $V_{OL} \approx 0.2\text{V}$), while pulling the base of $Q_3$ Low, turning $Q_3$ Off. ``` +Vcc (5V) | [R] | +--+---+ | | [R] [R] | | B1 | +-----+ | | | +-/-\-+ Q2| [ ] Q3 (Pull-up) A ----- E1 | Q1 |---|----+| B ----- E2 | | | | \ +-----+ | +--|>| (Diode D1) | | | +-[R]--+ +-----+---- Output | | | / \ +---| Q4| (Pull-down) \ / +-- | GND ``` ### 2.2 Open Collector TTL - Removes the active pull-up transistor $Q_3$, diode $D_1$, and resistor. - **Requires an external pull-up resistor** ($R_P$) to function. - **Advantage**: Allows **Wired-AND** connection (connecting outputs together creates a logical AND of outputs without damage). - **Disadvantage**: Slower due to RC time constant of pull-up resistor and load capacitance. ### 2.3 Three-State (Tri-State) Output Logic - Features three output states: **Logic 0 (Low)**, **Logic 1 (High)**, and **High-Impedance (Hi-Z)**. - **Hi-Z state**: Both totem-pole transistors ($Q_3$ and $Q_4$) are turned Off simultaneously by an external Enable input. - Essential for sharing a common communication bus by preventing bus contention (short circuits). ### 2.4 TTL Subfamilies - **74**: Standard TTL (medium speed/power). - **74L / 74H**: Low Power (high resistors) / High Speed (low resistors). - **74S (Schottky)**: Uses Schottky transistors with clamp diodes to prevent saturation, eliminating storage delay. Fastest bipolar family. - **74LS (Low-power Schottky)**: Combines Schottky speed with lower power. - **74ALS (Advanced Low-power Schottky)**: Best overall speed-power product. --- ## 3. MOS & CMOS Logic Families Unipolar logic families use MOSFETs (PMOS, NMOS) or complementary MOSFETs (CMOS). ### 3.1 CMOS Structure (Complementary MOS) - Consists of a **PMOS Pull-Up Network (PUN)** and an **NMOS Pull-Down Network (PDN)**. - **PMOS**: Conducts when Gate is Low ($0$). Connected to $V_{DD}$. - **NMOS**: Conducts when Gate is High ($1$). Connected to $V_{SS}$ (GND). - **Static Power Dissipation**: Effectively **zero**, because in either state, one network is completely Off. Power is only dissipated during high-frequency switching. ### 3.2 Realization of CMOS Inverter, NAND, and NOR ``` CMOS Inverter CMOS NAND CMOS NOR +Vdd +Vdd +Vdd | | | o-[ ]- PMOS +-+-+ o-[ ]- PMOS (A) A -| | A --o--[ ] [ ]--o-- PMOS | +-+-+ | | | | | | o-[ ]- PMOS (B) | B | +-+-+-+-+ | +----- Output | | | +-----+---- Output | +----+---+ | | +-+-+ | | | A -| | A ------[ ]- NMOS -[ ]- -[ ]- NMOS (A & B) o-[ ]- NMOS | | | | B ------[ ]- NMOS +-----+ GND | | GND GND ``` * **CMOS NAND**: PMOS are in parallel; NMOS are in series. * **CMOS NOR**: PMOS are in series; NMOS are in parallel. --- ## 4. Realization of Logic Gates in Various Families ### 4.1 Resistor-Transistor Logic (RTL) - First commercial family, uses resistors and BJTs. - **RTL NOR Gate**: Inputs are fed to bases of parallel BJTs through input resistors. If any input is High, its transistor saturates, pulling the collector output Low to GND. ### 4.2 Diode-Transistor Logic (DTL) - Uses diodes for the logical AND operation, followed by a BJT inverter. - **DTL NAND Gate**: Inputs $A, B$ connected to cathodes of diodes. An anode node connects through a resistor to $V_{CC}$. If any input is Low, current is diverted away from the BJT base, turning it Off (Output is High). ### 4.3 Emitter-Coupled Logic (ECL) - Fastest Bipolar Family - Uses a **differential amplifier** (current-steering) configuration. - **Non-saturated**: Transistors never saturate, completely eliminating storage time delay. - **Features**: - Extremely fast ($t_{pd} \approx 0.5\text{ ns}$ to $1\text{ ns}$). - High power dissipation (current constantly flows). - Low noise margin, differential outputs (OR/NOR available simultaneously). - Uses negative power supply ($V_{EE} = -5.2\text{V}$) to minimize noise. --- ## 5. Comparison of Major Logic Families | Parameter | Standard TTL | Schottky TTL (74S) | CMOS (74HC) | ECL | | :--- | :---: | :---: | :---: | :---: | | **BJT / FET** | Bipolar | Bipolar | Unipolar (FET) | Bipolar | | **Propagation Delay** | $10\text{ ns}$ | $3\text{ ns}$ | $8\text{ ns}$ | $1\text{ ns}$ (Fastest) | | **Power Dissipation (Static)**| $10\text{ mW}$ | $20\text{ mW}$ | $\approx 0.1\text{ }\mu\text{W}$ (Lowest)| $40\text{ mW}$ (Highest)| | **Fan-Out** | $10$ | $10$ | $>50$ | $25$ | | **Noise Margin** | $0.4\text{ V}$ | $0.4\text{ V}$ | $1.5\text{ V}$ (High) | $0.25\text{ V}$ (Lowest) | | **Figure of Merit (pJ)** | $100$ | $60$ | $0.001$ (Excellent) | $40$ | --- ## 6. Exam Tips & Common Pitfalls > [!WARNING] > - **Wired-AND Danger**: Connecting totem-pole TTL outputs together directly is dangerous. If one output is High and the other is Low, a low-impedance short circuit path is created, drawing excessive current and destroying the ICs. Use Open Collector outputs for Wired-AND. > - **Unused Inputs**: > - **TTL**: Floating inputs float to Logic 1, but are prone to picking up noise. Connect unused inputs to $V_{CC}$ through a $1\text{ k}\Omega$ pull-up resistor or tie them to a used input. > - **CMOS**: Floating gates can collect electrostatic charge, causing PMOS and NMOS to conduct simultaneously, overheating the chip. **CMOS inputs must NEVER be left floating.** Tie them to $V_{DD}$ or GND. > - **ECL Speed Secret**: ECL is fast because it operates in the active (linear) region, steering current rather than turning transistors fully On (saturated) and Off.

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Topic 56 Key Rules

Digital Logic Systems Unit 4: Combinational Circuits

# Unit 4: Combinational Circuits Combinational logic circuits are digital blocks whose outputs at any time depend only on the combination of inputs present at that exact moment. They do not possess feedback loops or memory elements. --- ## 1. General Design Methodology To design any combinational circuit: 1. **Specify the Problem**: Define the system requirements. 2. **Determine Inputs and Outputs**: Assign variables to inputs and outputs. 3. **Formulate the Truth Table**: List all possible input combinations and corresponding outputs. 4. **Simplify Expressions**: Use K-maps or Boolean theorems to find the minimized logic expressions. 5. **Realize the Circuit**: Draw the logic diagram using appropriate gates. --- ## 2. Arithmetic Circuits ### 2.1 Half Adder (HA) & Full Adder (FA) * **Half Adder**: Adds two 1-bit numbers ($A, B$). - **Sum ($S$)**: $A \oplus B = A'B + AB'$ - **Carry ($C$)**: $A \cdot B$ * **Full Adder**: Adds three 1-bit numbers ($A, B, C_{in}$). - **Sum ($S$)**: $A \oplus B \oplus C_{in}$ - **Carry-out ($C_{out}$)**: $AB + BC_{in} + AC_{in} = AB + C_{in}(A \oplus B)$ - **Realization using 2 Half Adders**: - $HA_1 \rightarrow S_1 = A \oplus B$, \ $C_1 = AB$ - $HA_2 \rightarrow S = S_1 \oplus C_{in} = A \oplus B \oplus C_{in}$, \ $C_2 = S_1 \cdot C_{in}$ - Combined Carry: $C_{out} = C_1 + C_2 = AB + C_{in}(A \oplus B)$ ``` Full Adder using 2 Half Adders: A ----+---------+ | | [HA 1] B ----+--+------|-----\ (Sum1) | | | XOR )-----+-------\ | | +---|-----/ | | [HA 2] | | | | | +---|-----\ (Sum) | | | | | | | XOR)----------- Sum (S) | | | | [AND] | | +-|-----/ | | | +---( )--+ | | | | | | +-------( ) | | | | | [AND] | | | | +-|-|--( )--+ | +---------------|----+ | | ( ) | | | Cin --+ | | +------------------|------------+ | +---+ | +---|OR |---- Carry (Cout) +------------------------| | +---+ ``` ### 2.2 Half Subtractor (HS) & Full Subtractor (FS) * **Half Subtractor**: Computes $A - B$. - **Difference ($D$)**: $A \oplus B$ - **Borrow ($B_{out}$)**: $A'B$ * **Full Subtractor**: Computes $A - B - B_{in}$. - **Difference ($D$)**: $A \oplus B \oplus B_{in}$ - **Borrow ($B_{out}$)**: $A'B + B_{in}(A \oplus B)' = A'B + B_{in}(A'B' + AB) = A'B + B_{in}(A \oplus B)'$ ### 2.3 BCD Adder A BCD digit can only range from $0$ to $9$ ($0000$ to $1001$). Adding two BCD digits can yield a sum up to $19$ ($9+9+1 \text{ carry}$). * **Structure**: Uses a standard 4-bit binary adder to compute the raw sum ($S_3 S_2 S_1 S_0$) and carry ($K$). * **Correction Rule**: If the raw sum is greater than $9$ or if a carry $K = 1$ is generated, it represents an invalid BCD code. - **Detection logic**: $$Y = K + S_3S_2 + S_3S_1$$ - If $Y = 1$, the sum is invalid. Add $6$ ($0110_2$) to the raw sum using a second 4-bit binary adder to bypass the 6 invalid states ($10$ to $15$). - The final output carry is $C_{out} = Y$. ``` A [4] B [4] | | +--v----------v--+ | 4-Bit Binary |---- Raw Carry (K) | Adder (Stage 1)| +-------+--------+ | Raw Sum [4] (S3 S2 S1 S0) +--------+-------+ | | | | +---+ | | | Y |<----+ (Y = K + S3•S2 + S3•S1) | +---+ | | Correct? (Y = 1 means add 0110, Y = 0 means add 0000) | v +--v--------v----+ | 4-Bit Binary | | Adder (Stage 2)| +-------+--------+ | v Final BCD Sum [4] ``` --- ## 3. Data Routing & Conversion Circuits ### 3.1 Decoders A decoder converts binary information from $n$ inputs to a maximum of $2^n$ unique outputs. * **3-to-8 Decoder (Binary-to-Octal)**: Inputs $A, B, C$. Outputs $D_0$ to $D_7$. - Output equation for active-high: $D_i = m_i$ (minterm). - Typically includes an active-low **Enable ($E$)** input. If $E=1$, all outputs are inactive (High/Low depending on polarity). ### 3.2 Encoders & Priority Encoders An encoder performs the inverse operation of a decoder, receiving $2^n$ inputs and producing an $n$-bit binary code. * **Problem**: In a basic encoder, if two inputs are active simultaneously, the output is corrupted. * **Solution (Priority Encoder)**: If multiple inputs are active, only the input with the highest priority is encoded. * **4-to-2 Priority Encoder**: Inputs $D_3$ (highest priority), $D_2, D_1, D_0$. Outputs $X, Y$ and Validity $V$ (indicates if any input is active). | $D_3$ | $D_2$ | $D_1$ | $D_0$ | $X$ | $Y$ | $V$ | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | $0$ | $0$ | $0$ | $0$ | $X$ | $X$ | $0$ | | $0$ | $0$ | $0$ | $1$ | $0$ | $0$ | $1$ | | $0$ | $0$ | $1$ | $X$ | $0$ | $1$ | $1$ | | $0$ | $1$ | $X$ | $X$ | $1$ | $0$ | $1$ | | $1$ | $X$ | $X$ | $X$ | $1$ | $1$ | $1$ | *Equations*: - $X = D_3 + D_2$ - $Y = D_3 + D_2'D_1$ - $V = D_3 + D_2 + D_1 + D_0$ ### 3.3 BCD to 7-Segment Decoder Converts a BCD code to drive a 7-segment display (composed of LEDs $a, b, c, d, e, f, g$). * **Configurations**: - **Common Anode**: All anodes tied to $V_{CC}$. Display segments light up on Low ($0$) signals (e.g., IC 7447). - **Common Cathode**: All cathodes tied to GND. Display segments light up on High ($1$) signals (e.g., IC 7448). ``` a +-----+ f | | b +--g--+ e | | c +-----+ . dp d ``` ### 3.4 Multiplexers (MUX / Data Selectors) A multiplexer routes data from one of $2^n$ inputs to a single output based on $n$ select lines. * **4-to-1 Multiplexer**: Inputs $I_0, I_1, I_2, I_3$, Select lines $S_1, S_0$. - Output Equation: $$Y = S_1'S_0'I_0 + S_1'S_0I_1 + S_1S_0'I_2 + S_1S_0I_3$$ #### Realization of Boolean Functions using MUX An $n$-variable Boolean function can be implemented using a $2^{n-1}$-to-1 MUX ($n-1$ select lines): 1. Connect $n-1$ variables to the select lines of the MUX. 2. Express the inputs of the MUX in terms of the remaining single variable (say, $Z$), which can take values: $0$, $1$, $Z$, or $Z'$. 3. *Example*: Implement $F(A,B,C) = \sum m(1, 2, 6, 7)$ using a 4-to-1 MUX. - Let $A, B$ be select inputs $S_1, S_0$. - For $AB = 00$ (covers $m_0, m_1$): $F(0,0,0)=0, F(0,0,1)=1 \rightarrow I_0 = C$. - For $AB = 01$ (covers $m_2, m_3$): $F(0,1,0)=1, F(0,1,1)=0 \rightarrow I_1 = C'$. - For $AB = 10$ (covers $m_4, m_5$): $F(1,0,0)=0, F(1,0,1)=0 \rightarrow I_2 = 0$. - For $AB = 11$ (covers $m_6, m_7$): $F(1,1,0)=1, F(1,1,1)=1 \rightarrow I_3 = 1$. ### 3.5 Demultiplexers (DEMUX / Data Distributors) A demultiplexer receives data on a single input line and routes it to one of $2^n$ outputs based on $n$ select lines. - A decoder with an Enable line acts exactly as a demultiplexer (Enable line serves as the single data input). --- ## 4. Exam Tips & Common Pitfalls > [!WARNING] > - **BCD Adder Correction Check**: Do not forget to apply the $+0110_2$ correction logic to BCD addition whenever a decimal carry ($K=1$) is generated, even if the raw sum is less than 9 (e.g., $8 + 8 = 16_d$, raw sum is $0000$ with carry $1$, correction yields $0110$ with carry $1$ which is $16$ in BCD). > - **MUX Implementation Variable Selection**: The variable placed on the input lines should ideally be the least significant variable to maintain standard minterm numbering.

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Digital Logic Systems Unit 5: Sequential Circuits

# Unit 5: Sequential Circuits Unlike combinational circuits, sequential circuits contain memory elements that store the system's "current state." Their outputs at any time depend on both current inputs and the history of past inputs (state). --- ## 1. Latches vs. Flip-Flops * **Latch**: A level-sensitive storage element. It changes state as long as the enable signal is at a specific active level (transparent mode). * **Flip-Flop (FF)**: An edge-triggered storage element. It changes state only at the rising (positive) or falling (negative) edge of a clock signal. --- ## 2. Core Flip-Flops & Excitation Tables ### 2.1 SR (Set-Reset) Flip-Flop - **Inputs**: $S$ (Set), $R$ (Reset). - **Invalid State**: $S=R=1$ leads to an unstable/undefined output when clock goes low. - **Characteristic Equation**: $$Q_{next} = S + R'Q \quad (\text{with constraint } SR = 0)$$ ### 2.2 JK Flip-Flop - Resolves the invalid state of the SR flip-flop by toggling the output when $J=K=1$. - **Characteristic Equation**: $$Q_{next} = JQ' + K'Q$$ - **The Race-Around Condition**: - *Definition*: In a level-triggered JK flip-flop, if $J = K = 1$ and the clock pulse width $t_w$ is larger than the gate propagation delay $t_{pd}$, the output will toggle continuously and unpredictably during the clock high period. - *Remedies*: 1. Use edge-triggered flip-flops. 2. Ensure clock pulse width $t_w < t_{pd}$. 3. Use a **Master-Slave JK Flip-Flop**. ### 2.3 Master-Slave JK Flip-Flop - Consists of two cascaded JK flip-flops: - **Master**: Enabled when Clock is High. It samples inputs and updates its state. - **Slave**: Enabled when Clock is Low (fed with inverted clock). It copies the master's state to the main outputs. - Since the slave only updates when Clock goes Low, the output changes exactly once per clock cycle, eliminating the race-around condition. ### 2.4 D (Delay / Data) Flip-Flop - Directly copies the input $D$ at the clock edge. - **Characteristic Equation**: $$Q_{next} = D$$ ### 2.5 T (Toggle) Flip-Flop - Toggles the state if $T=1$, holds state if $T=0$. - **Characteristic Equation**: $$Q_{next} = T \oplus Q = TQ' + T'Q$$ --- ## 3. Summary Tables of Flip-Flops ### 3.1 Characteristic Tables Shows the next state $Q_{next}$ based on inputs and current state $Q$. | Input (SR) | $Q_{next}$ | Input (JK) | $Q_{next}$ | Input (D) | $Q_{next}$ | Input (T) | $Q_{next}$ | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | $S=0, R=0$ | $Q$ (Hold) | $J=0, K=0$ | $Q$ (Hold) | $D=0$ | $0$ (Reset)| $T=0$ | $Q$ (Hold) | | $S=0, R=1$ | $0$ (Reset)| $J=0, K=1$ | $0$ (Reset)| $D=1$ | $1$ (Set) | $T=1$ | $Q'$ (Toggle)| | $S=1, R=0$ | $1$ (Set) | $J=1, K=0$ | $1$ (Set) | | | | | | $S=1, R=1$ | Invalid | $J=1, K=1$ | $Q'$ (Toggle)| | | | | ### 3.2 Excitation Tables Indicates the required inputs to transition from a current state $Q$ to a desired next state $Q_{next}$. *Crucial for counter and sequential circuit design.* | Current ($Q$) | Desired ($Q_{next}$) | $S$ | $R$ | $J$ | $K$ | $D$ | $T$ | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | $0$ | $0$ | $0$ | $X$ | $0$ | $X$ | $0$ | $0$ | | $0$ | $1$ | $1$ | $0$ | $1$ | $X$ | $1$ | $1$ | | $1$ | $0$ | $0$ | $1$ | $X$ | $1$ | $0$ | $1$ | | $1$ | $1$ | $X$ | $0$ | $X$ | $0$ | $1$ | $0$ | --- ## 4. Registers and Shift Registers A **register** is a group of flip-flops used to store multiple bits of binary data. A **shift register** is capable of shifting binary data left or right. ### 4.1 Four Basic Configurations 1. **SISO (Serial-In Serial-Out)**: Data entered one bit per clock cycle, read out one bit per clock cycle. Needs $N$ clock cycles for loading, $N-1$ for retrieval. 2. **SIPO (Serial-In Parallel-Out)**: Serial input, all outputs available immediately. Needs $N$ clock cycles to load. 3. **PISO (Parallel-In Serial-Out)**: Parallel load (in 1 clock cycle), serial shift out (needs $N-1$ clock cycles). 4. **PIPO (Parallel-In Parallel-Out)**: Data loaded and read simultaneously (1 clock cycle). ### 4.2 Shift Register Counters * **Ring Counter**: A circular shift register where the output of the last stage ($Q_N$) is connected to the input of the first stage ($D_0$). A single preset '1' circulates. - Number of states for $N$ flip-flops = $N$. - Uses simple decoding logic but has a low state density. * **Johnson Counter (Twisted Ring Counter)**: The inverted output of the last stage ($Q_N'$) is connected to the input of the first stage ($D_0$). - Number of states for $N$ flip-flops = $2N$. - Example: A 4-bit Johnson counter counts through $8$ states ($0000 \rightarrow 1000 \rightarrow 1100 \rightarrow 1110 \rightarrow 1111 \rightarrow 0111 \rightarrow 0011 \rightarrow 0001 \rightarrow \text{repeat}$). --- ## 5. Counters Counters are sequential circuits that cycle through a predefined sequence of states. ### Asynchronous (Ripple) vs. Synchronous Counters * **Asynchronous Counters**: - The clock input is connected only to the first flip-flop. Subsequent flip-flops are clocked by the outputs of preceding flip-flops. - **Propagation Delay accumulates**: $T_{total} = N \cdot t_{pd}$. This limits the maximum operating frequency. * **Synchronous Counters**: - All flip-flops are connected to a common clock signal and trigger simultaneously. - Slower propagation delays are avoided, allowing much higher operating frequencies. ### 5.1 Synchronous Counter Design Methodology 1. **Define State Sequence**: Draw the State Transition Diagram. 2. **Construct State Table**: Show present state ($Q_A, Q_B, ...$) and next state ($Q_A^+, Q_B^+, ...$). 3. **Incorporate Excitation Table**: Determine required input excitations for each flip-flop ($J_A, K_A, ...$) using the Excitation Table. 4. **Solve Excitation Equations**: Use K-maps to minimize input expressions in terms of present states. 5. **Draw the Circuit**: Realize using flip-flops and logic gates. ### 5.2 Synchronous Up/Down Counter Uses a mode control input $M$ to steer the clock or inputs: - If $M=0$, it counts UP (e.g., $Q_{next}$ determined by $Q$ terms). - If $M=1$, it counts DOWN (e.g., $Q_{next}$ determined by $Q'$ terms). ### 5.3 Programmable Counters (Mod-N Counters) Counters that reset to zero (or load a preset value) after reaching a count $N$. - **Asynchronous Mod-N**: Uses NAND gate feedback connected to the asynchronous **CLEAR** inputs of the flip-flops. When the binary value corresponding to $N$ appears, the NAND gate output goes Low, resetting the counter to $0$. - **Synchronous Mod-N**: Incorporates feedback gates directly into the $D$ or $J\text{-}K$ inputs so the reset occurs synchronously on the next clock pulse. --- ## 6. Finite State Machines (FSM): Mealy vs. Moore Sequential circuits can be represented mathematically as FSMs. ### 6.1 Mealy Machine - Outputs depend on **both the present state and the current inputs**. - If inputs change, outputs can change immediately (asynchronously), even without a clock edge. - Generally requires fewer states than a Moore machine to implement the same logic. ``` Inputs ----+------------------+ | v | +-------------+ | +------------+ | | Combinational| | | Output | | | Next-State | +->| Logic |----> Outputs | | Logic | +------------+ | +-------------+ ^ v | | +------------------+ | | v | | +------------------------------+ | | | State Register (Memory) |--+ | +------------------------------+ +------------------+ ``` ### 6.2 Moore Machine - Outputs depend **only on the present state**. - Outputs are synchronous with the clock. - Easier to design and analyze since outputs are stable during input transitions. ``` Inputs ------>+-------------+ | Combinational| | Next-State | | Logic | +-------------+ | v +---------------+ | State Register|-----+-----> [Output Logic] ----> Outputs +---------------+ | ^ | +-------------+ ``` --- ## 7. Exam Tips & Common Pitfalls > [!WARNING] > - **Self-Starting Counters**: When designing counters, check what happens if the circuit powers up in an unused state (e.g., states $5, 6, 7$ in a Mod-5 counter). A robust design must ensure that the counter eventually enters the valid count cycle (self-starting), rather than getting locked in unused states. > - **Mealy Output Glitches**: Since Mealy outputs respond directly to inputs, any glitch/noise on the inputs can immediately produce a glitch on the output. Moore outputs are filtered by the state register flip-flops and are glitch-free.

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High-Yield Practice Questions

Sample practice MCQs with step-by-step verified explanations.

Problem #1MEDIUM

2 से बारंबार भाग विधि का प्रयोग ______ से ______ में बदलने के लिए किया जाता है।

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Problem #2MEDIUM

द्विआधारी अंक में सबसे दायीं ओर का द्वयंक है _______ ।

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Problem #3MEDIUM

'+' कैरेक्टर की आसकी कोड (ASCII CODE) क्या है

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Problem #4MEDIUM

सूची-1 को सूची-II से सुमेलित कीजिए :सूची-I (दशमलव मूल्य)सूची-II (द्विचर मूल्य)a. 4 I. 1000b. 5 II. 1001c. 9 III. 0101d. 8 IV. 0100नीचे दिए गए विकल्पों में से सही उत्तर चुनिए:

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Problem #5MEDIUM

अष्ट आधारी संख्या पद्धति में आधार होता है ____।

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Problem #6MEDIUM

कम्प्यूटर में बाइनरी प्रणाली के अन्तर्गत कितने अंक उपयोग में आते हैं -

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Problem #7MEDIUM

द्विआधारी अंक _______ को 11 से भाग देने पर, आउटपुट 10 होता है। सही विकल्प को पहचानें।

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Problem #8MEDIUM

भिन्नात्मक संख्या 0.1011 का दाशमिक संख्या में बदलें। सही उत्तर चुनें।

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