# Unit 3: Digital Logic Gate Characteristics & Families Digital circuits are built using integrated circuits (ICs) classified into logic families based on their internal circuitry and device technology. This unit covers logic gate parameters, Transistor-Transistor Logic (TTL), Complementary Metal-Oxide-Semiconductor (CMOS) logic, and implementations using RTL, DTL, ECL, and MOS. --- ## 1. Digital Logic Gate Characteristics To compare different logic families, we evaluate specific electronic performance metrics: 1. **Propagation Delay ($t_{pd}$)**: The average time delay between input transition and output transition. Measured at $50\%$ voltage levels. - $t_{pHL}$: Delay from High to Low transition. - $t_{pLH}$: Delay from Low to High transition. - $t_{pd} = \frac{t_{pHL} + t_{pLH}}{2}$ 2. **Power Dissipation ($P_D$)**: The amount of power consumed by a gate. - Static Power: Consumed when state is idle. - Dynamic Power: Consumed during transitions (charging/discharging parasitic capacitances). 3. **Fan-Out**: The maximum number of inputs of the *same* logic family that a gate output can reliably drive without violating logic levels. - $\text{Fan-Out} = \min\left( \frac{I_{OH}}{I_{IH}}, \frac{I_{OL}}{I_{IL}} \right)$ 4. **Noise Margin ($NM$)**: The measure of a gate's noise immunity. - **High-Level Noise Margin**: $NM_H = V_{OH(min)} - V_{IH(min)}$ - **Low-Level Noise Margin**: $NM_L = V_{IL(max)} - V_{OL(max)}$ 5. **Figure of Merit (FOM)**: Product of speed and power: $$\text{FOM} = \text{Propagation Delay} \ (\text{ns}) \times \text{Power Dissipation} \ (\text{mW}) \quad [\text{unit: picoJoules, pJ}]$$ *A lower Figure of Merit represents a superior technology.* --- ## 2. Transistor-Transistor Logic (TTL) TTL is a bipolar logic family. The basic TTL gate is a **NAND gate**. ### 2.1 Operation of Totem-Pole TTL NAND Gate A standard TTL NAND gate consists of four stages: 1. **Input Stage (Multi-Emitter Transistor $Q_1$)**: Replaces input diodes of DTL. If any input $A$ or $B$ is Low ($0.2\text{V}$), $Q_1$'s base-emitter junction is forward-biased. $Q_1$ is saturated, pulling the base of Phase-Splitter $Q_2$ Low, turning it Off. 2. **Phase-Splitter Stage ($Q_2$)**: Splitting transistor. Since $Q_2$ is Off, no current flows to $Q_4$ (pull-down), so $Q_4$ is Off. The collector of $Q_2$ rises toward $V_{CC}$, turning $Q_3$ On. 3. **Active Pull-Up / Totem-Pole Output ($Q_3$, Diode $D_1$, $Q_4$)**: - **When Output is High**: $Q_3$ acts as an emitter follower, sourcing current to the load. Diode $D_1$ ensures $Q_3$ stays Off when output is Low. - **When Output is Low**: (Both inputs $A, B$ are High): $Q_1$ is reverse-active. Current flows into the base of $Q_2$, saturating it. $Q_2$ turns $Q_4$ On (saturating it to pull the output Low to $V_{OL} \approx 0.2\text{V}$), while pulling the base of $Q_3$ Low, turning $Q_3$ Off. ``` +Vcc (5V) | [R] | +--+---+ | | [R] [R] | | B1 | +-----+ | | | +-/-\-+ Q2| [ ] Q3 (Pull-up) A ----- E1 | Q1 |---|----+| B ----- E2 | | | | \ +-----+ | +--|>| (Diode D1) | | | +-[R]--+ +-----+---- Output | | | / \ +---| Q4| (Pull-down) \ / +-- | GND ``` ### 2.2 Open Collector TTL - Removes the active pull-up transistor $Q_3$, diode $D_1$, and resistor. - **Requires an external pull-up resistor** ($R_P$) to function. - **Advantage**: Allows **Wired-AND** connection (connecting outputs together creates a logical AND of outputs without damage). - **Disadvantage**: Slower due to RC time constant of pull-up resistor and load capacitance. ### 2.3 Three-State (Tri-State) Output Logic - Features three output states: **Logic 0 (Low)**, **Logic 1 (High)**, and **High-Impedance (Hi-Z)**. - **Hi-Z state**: Both totem-pole transistors ($Q_3$ and $Q_4$) are turned Off simultaneously by an external Enable input. - Essential for sharing a common communication bus by preventing bus contention (short circuits). ### 2.4 TTL Subfamilies - **74**: Standard TTL (medium speed/power). - **74L / 74H**: Low Power (high resistors) / High Speed (low resistors). - **74S (Schottky)**: Uses Schottky transistors with clamp diodes to prevent saturation, eliminating storage delay. Fastest bipolar family. - **74LS (Low-power Schottky)**: Combines Schottky speed with lower power. - **74ALS (Advanced Low-power Schottky)**: Best overall speed-power product. --- ## 3. MOS & CMOS Logic Families Unipolar logic families use MOSFETs (PMOS, NMOS) or complementary MOSFETs (CMOS). ### 3.1 CMOS Structure (Complementary MOS) - Consists of a **PMOS Pull-Up Network (PUN)** and an **NMOS Pull-Down Network (PDN)**. - **PMOS**: Conducts when Gate is Low ($0$). Connected to $V_{DD}$. - **NMOS**: Conducts when Gate is High ($1$). Connected to $V_{SS}$ (GND). - **Static Power Dissipation**: Effectively **zero**, because in either state, one network is completely Off. Power is only dissipated during high-frequency switching. ### 3.2 Realization of CMOS Inverter, NAND, and NOR ``` CMOS Inverter CMOS NAND CMOS NOR +Vdd +Vdd +Vdd | | | o-[ ]- PMOS +-+-+ o-[ ]- PMOS (A) A -| | A --o--[ ] [ ]--o-- PMOS | +-+-+ | | | | | | o-[ ]- PMOS (B) | B | +-+-+-+-+ | +----- Output | | | +-----+---- Output | +----+---+ | | +-+-+ | | | A -| | A ------[ ]- NMOS -[ ]- -[ ]- NMOS (A & B) o-[ ]- NMOS | | | | B ------[ ]- NMOS +-----+ GND | | GND GND ``` * **CMOS NAND**: PMOS are in parallel; NMOS are in series. * **CMOS NOR**: PMOS are in series; NMOS are in parallel. --- ## 4. Realization of Logic Gates in Various Families ### 4.1 Resistor-Transistor Logic (RTL) - First commercial family, uses resistors and BJTs. - **RTL NOR Gate**: Inputs are fed to bases of parallel BJTs through input resistors. If any input is High, its transistor saturates, pulling the collector output Low to GND. ### 4.2 Diode-Transistor Logic (DTL) - Uses diodes for the logical AND operation, followed by a BJT inverter. - **DTL NAND Gate**: Inputs $A, B$ connected to cathodes of diodes. An anode node connects through a resistor to $V_{CC}$. If any input is Low, current is diverted away from the BJT base, turning it Off (Output is High). ### 4.3 Emitter-Coupled Logic (ECL) - Fastest Bipolar Family - Uses a **differential amplifier** (current-steering) configuration. - **Non-saturated**: Transistors never saturate, completely eliminating storage time delay. - **Features**: - Extremely fast ($t_{pd} \approx 0.5\text{ ns}$ to $1\text{ ns}$). - High power dissipation (current constantly flows). - Low noise margin, differential outputs (OR/NOR available simultaneously). - Uses negative power supply ($V_{EE} = -5.2\text{V}$) to minimize noise. --- ## 5. Comparison of Major Logic Families | Parameter | Standard TTL | Schottky TTL (74S) | CMOS (74HC) | ECL | | :--- | :---: | :---: | :---: | :---: | | **BJT / FET** | Bipolar | Bipolar | Unipolar (FET) | Bipolar | | **Propagation Delay** | $10\text{ ns}$ | $3\text{ ns}$ | $8\text{ ns}$ | $1\text{ ns}$ (Fastest) | | **Power Dissipation (Static)**| $10\text{ mW}$ | $20\text{ mW}$ | $\approx 0.1\text{ }\mu\text{W}$ (Lowest)| $40\text{ mW}$ (Highest)| | **Fan-Out** | $10$ | $10$ | $>50$ | $25$ | | **Noise Margin** | $0.4\text{ V}$ | $0.4\text{ V}$ | $1.5\text{ V}$ (High) | $0.25\text{ V}$ (Lowest) | | **Figure of Merit (pJ)** | $100$ | $60$ | $0.001$ (Excellent) | $40$ | --- ## 6. Exam Tips & Common Pitfalls > [!WARNING] > - **Wired-AND Danger**: Connecting totem-pole TTL outputs together directly is dangerous. If one output is High and the other is Low, a low-impedance short circuit path is created, drawing excessive current and destroying the ICs. Use Open Collector outputs for Wired-AND. > - **Unused Inputs**: > - **TTL**: Floating inputs float to Logic 1, but are prone to picking up noise. Connect unused inputs to $V_{CC}$ through a $1\text{ k}\Omega$ pull-up resistor or tie them to a used input. > - **CMOS**: Floating gates can collect electrostatic charge, causing PMOS and NMOS to conduct simultaneously, overheating the chip. **CMOS inputs must NEVER be left floating.** Tie them to $V_{DD}$ or GND. > - **ECL Speed Secret**: ECL is fast because it operates in the active (linear) region, steering current rather than turning transistors fully On (saturated) and Off.