Digital Logic Systems Unit 4: Combinational Circuits

Subject: Digital Logic Systems

Explore combinational design flow, half/full adders and subtractors, BCD adders, decoders (and 7-segment drivers), encoders (priority), multiplexers, and demultiplexers.

Concept Summary

# Unit 4: Combinational Circuits Combinational logic circuits are digital blocks whose outputs at any time depend only on the combination of inputs present at that exact moment. They do not possess feedback loops or memory elements. --- ## 1. General Design Methodology To design any combinational circuit: 1. **Specify the Problem**: Define the system requirements. 2. **Determine Inputs and Outputs**: Assign variables to inputs and outputs. 3. **Formulate the Truth Table**: List all possible input combinations and corresponding outputs. 4. **Simplify Expressions**: Use K-maps or Boolean theorems to find the minimized logic expressions. 5. **Realize the Circuit**: Draw the logic diagram using appropriate gates. --- ## 2. Arithmetic Circuits ### 2.1 Half Adder (HA) & Full Adder (FA) * **Half Adder**: Adds two 1-bit numbers ($A, B$). - **Sum ($S$)**: $A \oplus B = A'B + AB'$ - **Carry ($C$)**: $A \cdot B$ * **Full Adder**: Adds three 1-bit numbers ($A, B, C_{in}$). - **Sum ($S$)**: $A \oplus B \oplus C_{in}$ - **Carry-out ($C_{out}$)**: $AB + BC_{in} + AC_{in} = AB + C_{in}(A \oplus B)$ - **Realization using 2 Half Adders**: - $HA_1 \rightarrow S_1 = A \oplus B$, \ $C_1 = AB$ - $HA_2 \rightarrow S = S_1 \oplus C_{in} = A \oplus B \oplus C_{in}$, \ $C_2 = S_1 \cdot C_{in}$ - Combined Carry: $C_{out} = C_1 + C_2 = AB + C_{in}(A \oplus B)$ ``` Full Adder using 2 Half Adders: A ----+---------+ | | [HA 1] B ----+--+------|-----\ (Sum1) | | | XOR )-----+-------\ | | +---|-----/ | | [HA 2] | | | | | +---|-----\ (Sum) | | | | | | | XOR)----------- Sum (S) | | | | [AND] | | +-|-----/ | | | +---( )--+ | | | | | | +-------( ) | | | | | [AND] | | | | +-|-|--( )--+ | +---------------|----+ | | ( ) | | | Cin --+ | | +------------------|------------+ | +---+ | +---|OR |---- Carry (Cout) +------------------------| | +---+ ``` ### 2.2 Half Subtractor (HS) & Full Subtractor (FS) * **Half Subtractor**: Computes $A - B$. - **Difference ($D$)**: $A \oplus B$ - **Borrow ($B_{out}$)**: $A'B$ * **Full Subtractor**: Computes $A - B - B_{in}$. - **Difference ($D$)**: $A \oplus B \oplus B_{in}$ - **Borrow ($B_{out}$)**: $A'B + B_{in}(A \oplus B)' = A'B + B_{in}(A'B' + AB) = A'B + B_{in}(A \oplus B)'$ ### 2.3 BCD Adder A BCD digit can only range from $0$ to $9$ ($0000$ to $1001$). Adding two BCD digits can yield a sum up to $19$ ($9+9+1 \text{ carry}$). * **Structure**: Uses a standard 4-bit binary adder to compute the raw sum ($S_3 S_2 S_1 S_0$) and carry ($K$). * **Correction Rule**: If the raw sum is greater than $9$ or if a carry $K = 1$ is generated, it represents an invalid BCD code. - **Detection logic**: $$Y = K + S_3S_2 + S_3S_1$$ - If $Y = 1$, the sum is invalid. Add $6$ ($0110_2$) to the raw sum using a second 4-bit binary adder to bypass the 6 invalid states ($10$ to $15$). - The final output carry is $C_{out} = Y$. ``` A [4] B [4] | | +--v----------v--+ | 4-Bit Binary |---- Raw Carry (K) | Adder (Stage 1)| +-------+--------+ | Raw Sum [4] (S3 S2 S1 S0) +--------+-------+ | | | | +---+ | | | Y |<----+ (Y = K + S3•S2 + S3•S1) | +---+ | | Correct? (Y = 1 means add 0110, Y = 0 means add 0000) | v +--v--------v----+ | 4-Bit Binary | | Adder (Stage 2)| +-------+--------+ | v Final BCD Sum [4] ``` --- ## 3. Data Routing & Conversion Circuits ### 3.1 Decoders A decoder converts binary information from $n$ inputs to a maximum of $2^n$ unique outputs. * **3-to-8 Decoder (Binary-to-Octal)**: Inputs $A, B, C$. Outputs $D_0$ to $D_7$. - Output equation for active-high: $D_i = m_i$ (minterm). - Typically includes an active-low **Enable ($E$)** input. If $E=1$, all outputs are inactive (High/Low depending on polarity). ### 3.2 Encoders & Priority Encoders An encoder performs the inverse operation of a decoder, receiving $2^n$ inputs and producing an $n$-bit binary code. * **Problem**: In a basic encoder, if two inputs are active simultaneously, the output is corrupted. * **Solution (Priority Encoder)**: If multiple inputs are active, only the input with the highest priority is encoded. * **4-to-2 Priority Encoder**: Inputs $D_3$ (highest priority), $D_2, D_1, D_0$. Outputs $X, Y$ and Validity $V$ (indicates if any input is active). | $D_3$ | $D_2$ | $D_1$ | $D_0$ | $X$ | $Y$ | $V$ | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | $0$ | $0$ | $0$ | $0$ | $X$ | $X$ | $0$ | | $0$ | $0$ | $0$ | $1$ | $0$ | $0$ | $1$ | | $0$ | $0$ | $1$ | $X$ | $0$ | $1$ | $1$ | | $0$ | $1$ | $X$ | $X$ | $1$ | $0$ | $1$ | | $1$ | $X$ | $X$ | $X$ | $1$ | $1$ | $1$ | *Equations*: - $X = D_3 + D_2$ - $Y = D_3 + D_2'D_1$ - $V = D_3 + D_2 + D_1 + D_0$ ### 3.3 BCD to 7-Segment Decoder Converts a BCD code to drive a 7-segment display (composed of LEDs $a, b, c, d, e, f, g$). * **Configurations**: - **Common Anode**: All anodes tied to $V_{CC}$. Display segments light up on Low ($0$) signals (e.g., IC 7447). - **Common Cathode**: All cathodes tied to GND. Display segments light up on High ($1$) signals (e.g., IC 7448). ``` a +-----+ f | | b +--g--+ e | | c +-----+ . dp d ``` ### 3.4 Multiplexers (MUX / Data Selectors) A multiplexer routes data from one of $2^n$ inputs to a single output based on $n$ select lines. * **4-to-1 Multiplexer**: Inputs $I_0, I_1, I_2, I_3$, Select lines $S_1, S_0$. - Output Equation: $$Y = S_1'S_0'I_0 + S_1'S_0I_1 + S_1S_0'I_2 + S_1S_0I_3$$ #### Realization of Boolean Functions using MUX An $n$-variable Boolean function can be implemented using a $2^{n-1}$-to-1 MUX ($n-1$ select lines): 1. Connect $n-1$ variables to the select lines of the MUX. 2. Express the inputs of the MUX in terms of the remaining single variable (say, $Z$), which can take values: $0$, $1$, $Z$, or $Z'$. 3. *Example*: Implement $F(A,B,C) = \sum m(1, 2, 6, 7)$ using a 4-to-1 MUX. - Let $A, B$ be select inputs $S_1, S_0$. - For $AB = 00$ (covers $m_0, m_1$): $F(0,0,0)=0, F(0,0,1)=1 \rightarrow I_0 = C$. - For $AB = 01$ (covers $m_2, m_3$): $F(0,1,0)=1, F(0,1,1)=0 \rightarrow I_1 = C'$. - For $AB = 10$ (covers $m_4, m_5$): $F(1,0,0)=0, F(1,0,1)=0 \rightarrow I_2 = 0$. - For $AB = 11$ (covers $m_6, m_7$): $F(1,1,0)=1, F(1,1,1)=1 \rightarrow I_3 = 1$. ### 3.5 Demultiplexers (DEMUX / Data Distributors) A demultiplexer receives data on a single input line and routes it to one of $2^n$ outputs based on $n$ select lines. - A decoder with an Enable line acts exactly as a demultiplexer (Enable line serves as the single data input). --- ## 4. Exam Tips & Common Pitfalls > [!WARNING] > - **BCD Adder Correction Check**: Do not forget to apply the $+0110_2$ correction logic to BCD addition whenever a decimal carry ($K=1$) is generated, even if the raw sum is less than 9 (e.g., $8 + 8 = 16_d$, raw sum is $0000$ with carry $1$, correction yields $0110$ with carry $1$ which is $16$ in BCD). > - **MUX Implementation Variable Selection**: The variable placed on the input lines should ideally be the least significant variable to maintain standard minterm numbering.

Key Revision Rules & Formulas

Combinational circuits: outputs depend strictly on current inputs; no feedback loops or memory.
Half Adder (Sum = A ⊕ B, Carry = AB) vs. Full Adder (Sum = A ⊕ B ⊕ Cin, Carry = AB + Cin(A ⊕ B)).
Full Adder implementation using 2 Half Adders and 1 OR gate.
BCD Adder: adds two BCD digits, applies +0110 correction if sum > 9 or carry generated (detected via Y = K + S3S2 + S3S1).
Priority Encoder: resolves multiple active inputs by encoding only the highest priority active index.
Multiplexer (MUX): selects one of 2^n inputs using n select lines. Can implement any n-variable function using a 2^(n-1)-to-1 MUX.

Common Exam Pitfalls

BCD Adder carry detection: forgetting that if the raw carry K=1 is generated, $+0110$ must be added even if raw sum < 9.
Common Anode vs. Common Cathode 7-segment pins: Common Anode requires active-low drivers (IC 7447); Common Cathode requires active-high drivers (IC 7448).

Sample Practice Questions

Question 1: In a combinational circuit, the output at any instant depends:

On the past states of the circuit.
Only on the input combination present at that instant.
On both past states and present inputs.
On the clock frequency.

Explanation: Combinational circuits do not contain memory elements or feedback loops, so their output is strictly a function of the current input combination.

Question 2: What are the outputs of a Half Adder when inputs are $A=1$ and $B=1$?

Sum = 0, Carry = 0
Sum = 1, Carry = 0
Sum = 0, Carry = 1
Sum = 1, Carry = 1

Explanation: For a Half Adder, Sum $S = A \oplus B = 1 \oplus 1 = 0$. Carry $C = A \cdot B = 1 \cdot 1 = 1$.

Question 3: The logic expression for the Sum output of a Full Adder is:

$A \oplus B \oplus C_{in}$
$AB + BC_{in} + AC_{in}$
$A + B + C_{in}$
$A \oplus B + C_{in}$

Explanation: The Sum of three bits in binary addition is equivalent to their parity (odd number of 1s), which is implemented by XORing the three variables: $S = A \oplus B \oplus C_{in}$.

Question 4: The simplified Carry-out ($C_{out}$) expression for a Full Adder is:

$A \oplus B \oplus C_{in}$
$AB + C_{in}(A \oplus B)$
$AB + A'C_{in}$
$A'B + BC_{in}$

Explanation: The standard sum-of-products for carry-out is $AB + BC_{in} + AC_{in}$. This can be factored as $AB + C_{in}(A + B) = AB + C_{in}(A \oplus B)$, which is efficient because the XOR term $A \oplus B$ is already calculated for the Sum output.

Question 5: How many Half Adders and OR gates are needed to construct a Full Adder?

1 Half Adder and 2 OR gates
2 Half Adders and 1 OR gate
2 Half Adders and 2 OR gates
3 Half Adders and 1 OR gate

Explanation: A Full Adder is implemented using two Half Adders. The first HA adds $A$ and $B$. The second HA adds the resulting sum to $C_{in}$. The final carry-out is the logical OR of the carries generated by both Half Adders (1 OR gate).

Question 6: The output equations of a Half Subtractor ($A - B$) are:

Difference = $A \oplus B$, Borrow = $A'B$
Difference = $A \oplus B$, Borrow = $AB'$
Difference = $A \cdot B$, Borrow = $A' + B$
Difference = $A'B$, Borrow = $A \oplus B$

Explanation: Difference $D = A \oplus B$. Borrow $B_{out}$ is active when subtracting $1$ from $0$, which corresponds to $A=0$ and $B=1 \rightarrow A'B$.

Question 7: For a Full Subtractor ($A - B - B_{in}$), the Borrow-out ($B_{out}$) equation is:

$A'B + B_{in}(A \oplus B)'$
$AB' + B_{in}(A \oplus B)$
$A'B + B_{in}(A \oplus B)$
$A'B' + B_{in}(A \oplus B)'$

Explanation: The full sum-of-products borrow-out is $A'B + A'B_{in} + BB_{in}$. It simplifies to $A'B + B_{in}(A' + B) = A'B + B_{in}(A \oplus B)'$.

Question 8: A BCD Adder is used to add:

Two binary numbers.
Two octal numbers.
Two BCD digits (values 0-9).
Floating-point numbers.

Explanation: A BCD Adder adds two 4-bit BCD digits and outputs a 4-bit BCD sum and a carry bit.

Question 9: What correction must be added to a BCD adder stage if the binary sum is $1101_2$ ($13_{10}$)?

$0011$ (3)
$0110$ (6)
$1001$ (9)
$0000$ (No correction)

Explanation: Since $1101_2$ is greater than $9$, it is an invalid BCD code. Adding $6$ ($0110_2$) corrects it: $1101 + 0110 = 10011 \rightarrow$ BCD output of $0011$ ($3_{d}$) with a carry of $1$, representing $13$.

Question 10: What is the Boolean expression to detect an invalid BCD sum ($S_3 S_2 S_1 S_0$ with stage carry $K$)?

$Y = K + S_3S_2 + S_3S_1$
$Y = K + S_3S_0 + S_2S_1$
$Y = S_3S_2S_1S_0$
$Y = K(S_3 + S_2)$

Explanation: An invalid BCD sum occurs if a carry $K$ is generated ($16$ or above), or if the sum is $10$ to $15$. Minterms $10$ ($1010$) to $15$ ($1111$) all have $S_3=1$ AND either $S_2=1$ (values $12\text{-}15$) OR $S_1=1$ (values $10, 11$). Thus: $Y = K + S_3S_2 + S_3S_1$.

Digital Logic SystemsTopic Cheat Sheet

Digital Logic Systems Unit 4: Combinational Circuits

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Digital Logic Systems Unit 4: Combinational Circuits

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Master Digital Logic Systems Unit 4: Combinational Circuits

Explore combinational design flow, half/full adders and subtractors, BCD adders, decoders (and 7-segment drivers), encoders (priority), multiplexers, and demultiplexers.

Concept Breakdown

Detailed technical explanation

Unit 4: Combinational Circuits

Combinational logic circuits are digital blocks whose outputs at any time depend only on the combination of inputs present at that exact moment. They do not possess feedback loops or memory elements.

1. General Design Methodology

To design any combinational circuit:

Specify the Problem: Define the system requirements.
Determine Inputs and Outputs: Assign variables to inputs and outputs.
Formulate the Truth Table: List all possible input combinations and corresponding outputs.
Simplify Expressions: Use K-maps or Boolean theorems to find the minimized logic expressions.
Realize the Circuit: Draw the logic diagram using appropriate gates.

2. Arithmetic Circuits

2.1 Half Adder (HA) & Full Adder (FA)

Half Adder: Adds two 1-bit numbers ( $A, B$ ).
- Sum ( $S$ ): $A \oplus B = A'B + AB'$
- Carry ( $C$ ): $A \cdot B$
Full Adder: Adds three 1-bit numbers ( $A, B, C_{in}$ ).
- Sum ( $S$ ): $A \oplus B \oplus C_{in}$
- Carry-out ( $C_{out}$ ): $AB + BC_{in} + AC_{in} = AB + C_{in}(A \oplus B)$
- Realization using 2 Half Adders:
  - $HA_1 \rightarrow S_1 = A \oplus B$ , \ $C_1 = AB$
  - $HA_2 \rightarrow S = S_1 \oplus C_{in} = A \oplus B \oplus C_{in}$ , \ $C_2 = S_1 \cdot C_{in}$
  - Combined Carry: $C_{out} = C_1 + C_2 = AB + C_{in}(A \oplus B)$

   Full Adder using 2 Half Adders:
    A ----+---------+
          |         | [HA 1]
    B ----+--+------|-----\    (Sum1)
          |  |      |   XOR )-----+-------\
          |  |  +---|-----/       |       | [HA 2]
          |  |  |   |             |   +---|-----\    (Sum)
          |  |  |   |             |   |   |   XOR)----------- Sum (S)
          |  |  |   | [AND]       |   | +-|-----/
          |  |  |   +---( )--+    |   | | |
          |  |  +-------( )  |    |   | | | [AND]
          |  |               |    |   +-|-|--( )--+
          |  +---------------|----+     | |  ( )  |
          |                  |    Cin --+ |       |
          +------------------|------------+       |   +---+
                             |                    +---|OR |---- Carry (Cout)
                             +------------------------|   |
                                                      +---+

2.2 Half Subtractor (HS) & Full Subtractor (FS)

Half Subtractor: Computes $A - B$ .
- Difference ( $D$ ): $A \oplus B$
- Borrow ( $B_{out}$ ): $A'B$
Full Subtractor: Computes $A - B - B_{in}$ .
- Difference ( $D$ ): $A \oplus B \oplus B_{in}$
- Borrow ( $B_{out}$ ): $A'B + B_{in}(A \oplus B)' = A'B + B_{in}(A'B' + AB) = A'B + B_{in}(A \oplus B)'$

2.3 BCD Adder

A BCD digit can only range from $0$ to $9$ ( $0000$ to $1001$ ). Adding two BCD digits can yield a sum up to $19$ ( $9+9+1 \text{ carry}$ ).

Structure: Uses a standard 4-bit binary adder to compute the raw sum ( $S_3 S_2 S_1 S_0$ ) and carry ( $K$ ).
Correction Rule: If the raw sum is greater than $9$ or if a carry $K = 1$ is generated, it represents an invalid BCD code.
- Detection logic: $Y = K + S_3S_2 + S_3S_1$
- If $Y = 1$ , the sum is invalid. Add $6$ ( $0110_2$ ) to the raw sum using a second 4-bit binary adder to bypass the 6 invalid states ( $10$ to $15$ ).
- The final output carry is $C_{out} = Y$ .

               A [4]      B [4]
                |          |
             +--v----------v--+
             | 4-Bit Binary   |---- Raw Carry (K)
             | Adder (Stage 1)|
             +-------+--------+
                     | Raw Sum [4] (S3 S2 S1 S0)
            +--------+-------+
            |        |       |
            |      +---+     |
            |      | Y |<----+ (Y = K + S3•S2 + S3•S1)
            |      +---+
            |        | Correct? (Y = 1 means add 0110, Y = 0 means add 0000)
            |        v
         +--v--------v----+
         | 4-Bit Binary   |
         | Adder (Stage 2)|
         +-------+--------+
                 |
                 v Final BCD Sum [4]

3. Data Routing & Conversion Circuits

3.1 Decoders

A decoder converts binary information from $n$ inputs to a maximum of $2^n$ unique outputs.

3-to-8 Decoder (Binary-to-Octal): Inputs $A, B, C$ . Outputs $D_0$ to $D_7$ .
- Output equation for active-high: $D_i = m_i$ (minterm).
- Typically includes an active-low Enable ( $E$ ) input. If $E=1$ , all outputs are inactive (High/Low depending on polarity).

3.2 Encoders & Priority Encoders

An encoder performs the inverse operation of a decoder, receiving $2^n$ inputs and producing an $n$ -bit binary code.

Problem: In a basic encoder, if two inputs are active simultaneously, the output is corrupted.
Solution (Priority Encoder): If multiple inputs are active, only the input with the highest priority is encoded.
4-to-2 Priority Encoder: Inputs $D_3$ (highest priority), $D_2, D_1, D_0$ . Outputs $X, Y$ and Validity $V$ (indicates if any input is active).

$D_3$	$D_2$	$D_1$	$D_0$	$X$	$Y$	$V$
$0$	$0$	$0$	$0$	$X$	$X$	$0$
$0$	$0$	$0$	$1$	$0$	$0$	$1$
$0$	$0$	$1$	$X$	$0$	$1$	$1$
$0$	$1$	$X$	$X$	$1$	$0$	$1$
$1$	$X$	$X$	$X$	$1$	$1$	$1$

Equations:

$X = D_3 + D_2$
$Y = D_3 + D_2'D_1$
$V = D_3 + D_2 + D_1 + D_0$

3.3 BCD to 7-Segment Decoder

Converts a BCD code to drive a 7-segment display (composed of LEDs $a, b, c, d, e, f, g$ ).

Configurations:
- Common Anode: All anodes tied to $V_{CC}$ . Display segments light up on Low ( $0$ ) signals (e.g., IC 7447).
- Common Cathode: All cathodes tied to GND. Display segments light up on High ( $1$ ) signals (e.g., IC 7448).

          a
       +-----+
     f |     | b
       +--g--+
     e |     | c
       +-----+ . dp
          d

3.4 Multiplexers (MUX / Data Selectors)

A multiplexer routes data from one of $2^n$ inputs to a single output based on $n$ select lines.

4-to-1 Multiplexer: Inputs $I_0, I_1, I_2, I_3$ , Select lines $S_1, S_0$ .
- Output Equation: $Y = S_1'S_0'I_0 + S_1'S_0I_1 + S_1S_0'I_2 + S_1S_0I_3$

Realization of Boolean Functions using MUX

An $n$ -variable Boolean function can be implemented using a $2^{n-1}$ -to-1 MUX ( $n-1$ select lines):

Connect $n-1$ variables to the select lines of the MUX.
Express the inputs of the MUX in terms of the remaining single variable (say, $Z$ ), which can take values: $0$ , $1$ , $Z$ , or $Z'$ .
Example: Implement $F(A,B,C) = \sum m(1, 2, 6, 7)$ using a 4-to-1 MUX.
- Let $A, B$ be select inputs $S_1, S_0$ .
- For $AB = 00$ (covers $m_0, m_1$ ): $F(0,0,0)=0, F(0,0,1)=1 \rightarrow I_0 = C$ .
- For $AB = 01$ (covers $m_2, m_3$ ): $F(0,1,0)=1, F(0,1,1)=0 \rightarrow I_1 = C'$ .
- For $AB = 10$ (covers $m_4, m_5$ ): $F(1,0,0)=0, F(1,0,1)=0 \rightarrow I_2 = 0$ .
- For $AB = 11$ (covers $m_6, m_7$ ): $F(1,1,0)=1, F(1,1,1)=1 \rightarrow I_3 = 1$ .

3.5 Demultiplexers (DEMUX / Data Distributors)

A demultiplexer receives data on a single input line and routes it to one of $2^n$ outputs based on $n$ select lines.

A decoder with an Enable line acts exactly as a demultiplexer (Enable line serves as the single data input).

4. Exam Tips & Common Pitfalls

[!WARNING]

BCD Adder Correction Check: Do not forget to apply the $+0110_2$ correction logic to BCD addition whenever a decimal carry ( $K=1$ ) is generated, even if the raw sum is less than 9 (e.g., $8 + 8 = 16_d$ , raw sum is $0000$ with carry $1$ , correction yields $0110$ with carry $1$ which is $16$ in BCD).

MUX Implementation Variable Selection: The variable placed on the input lines should ideally be the least significant variable to maintain standard minterm numbering.

Key Revision Rules

Essential formulas and core points to memorize

1Combinational circuits: outputs depend strictly on current inputs; no feedback loops or memory.
2Half Adder (Sum = A ⊕ B, Carry = AB) vs. Full Adder (Sum = A ⊕ B ⊕ Cin, Carry = AB + Cin(A ⊕ B)).
3Full Adder implementation using 2 Half Adders and 1 OR gate.
4BCD Adder: adds two BCD digits, applies +0110 correction if sum > 9 or carry generated (detected via Y = K + S3S2 + S3S1).
5Priority Encoder: resolves multiple active inputs by encoding only the highest priority active index.
6Multiplexer (MUX): selects one of 2^n inputs using n select lines. Can implement any n-variable function using a 2^(n-1)-to-1 MUX.

Common Exam Mistakes

Where students frequently lose marks

BCD Adder carry detection: forgetting that if the raw carry K=1 is generated, $+0110$ must be added even if raw sum < 9.

Common Anode vs. Common Cathode 7-segment pins: Common Anode requires active-low drivers (IC 7447); Common Cathode requires active-high drivers (IC 7448).

Topic Quiz Practice

1 of 10

Question 1

$D_3$	$D_2$	$D_1$	$D_0$	$X$	$Y$	$V$
$0$	$0$	$0$	$0$	$X$	$X$	$0$
$0$	$0$	$0$	$1$	$0$	$0$	$1$
$0$	$0$	$1$	$X$	$0$	$1$	$1$
$0$	$1$	$X$	$X$	$1$	$0$	$1$
$1$	$X$	$X$	$X$	$1$	$1$	$1$

$D_3$	$D_2$	$D_1$	$D_0$	$X$	$Y$	$V$
$0$	$0$	$0$	$0$	$X$	$X$	$0$
$0$	$0$	$0$	$1$	$0$	$0$	$1$
$0$	$0$	$1$	$X$	$0$	$1$	$1$
$0$	$1$	$X$	$X$	$1$	$0$	$1$
$1$	$X$	$X$	$X$	$1$	$1$	$1$

$D_3$	$D_2$	$D_1$	$D_0$	$X$	$Y$	$V$
$0$	$0$	$0$	$0$	$X$	$X$	$0$
$0$	$0$	$0$	$1$	$0$	$0$	$1$
$0$	$0$	$1$	$X$	$0$	$1$	$1$
$0$	$1$	$X$	$X$	$1$	$0$	$1$
$1$	$X$	$X$	$X$	$1$	$1$	$1$