Digital Logic Systems Unit 5: Sequential Circuits
Subject: Digital Logic Systems
Examine level vs. edge triggering, SR/JK/D/T flip-flops, Master-Slave JK race-around resolution, registers (SISO, SIPO, PISO, PIPO), Ring/Johnson counters, synchronous counter design flow, and Mealy/Moore FSMs.
Concept Summary
# Unit 5: Sequential Circuits
Unlike combinational circuits, sequential circuits contain memory elements that store the system's "current state." Their outputs at any time depend on both current inputs and the history of past inputs (state).
---
## 1. Latches vs. Flip-Flops
* **Latch**: A level-sensitive storage element. It changes state as long as the enable signal is at a specific active level (transparent mode).
* **Flip-Flop (FF)**: An edge-triggered storage element. It changes state only at the rising (positive) or falling (negative) edge of a clock signal.
---
## 2. Core Flip-Flops & Excitation Tables
### 2.1 SR (Set-Reset) Flip-Flop
- **Inputs**: $S$ (Set), $R$ (Reset).
- **Invalid State**: $S=R=1$ leads to an unstable/undefined output when clock goes low.
- **Characteristic Equation**:
$$Q_{next} = S + R'Q \quad (\text{with constraint } SR = 0)$$
### 2.2 JK Flip-Flop
- Resolves the invalid state of the SR flip-flop by toggling the output when $J=K=1$.
- **Characteristic Equation**:
$$Q_{next} = JQ' + K'Q$$
- **The Race-Around Condition**:
- *Definition*: In a level-triggered JK flip-flop, if $J = K = 1$ and the clock pulse width $t_w$ is larger than the gate propagation delay $t_{pd}$, the output will toggle continuously and unpredictably during the clock high period.
- *Remedies*:
1. Use edge-triggered flip-flops.
2. Ensure clock pulse width $t_w < t_{pd}$.
3. Use a **Master-Slave JK Flip-Flop**.
### 2.3 Master-Slave JK Flip-Flop
- Consists of two cascaded JK flip-flops:
- **Master**: Enabled when Clock is High. It samples inputs and updates its state.
- **Slave**: Enabled when Clock is Low (fed with inverted clock). It copies the master's state to the main outputs.
- Since the slave only updates when Clock goes Low, the output changes exactly once per clock cycle, eliminating the race-around condition.
### 2.4 D (Delay / Data) Flip-Flop
- Directly copies the input $D$ at the clock edge.
- **Characteristic Equation**:
$$Q_{next} = D$$
### 2.5 T (Toggle) Flip-Flop
- Toggles the state if $T=1$, holds state if $T=0$.
- **Characteristic Equation**:
$$Q_{next} = T \oplus Q = TQ' + T'Q$$
---
## 3. Summary Tables of Flip-Flops
### 3.1 Characteristic Tables
Shows the next state $Q_{next}$ based on inputs and current state $Q$.
| Input (SR) | $Q_{next}$ | Input (JK) | $Q_{next}$ | Input (D) | $Q_{next}$ | Input (T) | $Q_{next}$ |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| $S=0, R=0$ | $Q$ (Hold) | $J=0, K=0$ | $Q$ (Hold) | $D=0$ | $0$ (Reset)| $T=0$ | $Q$ (Hold) |
| $S=0, R=1$ | $0$ (Reset)| $J=0, K=1$ | $0$ (Reset)| $D=1$ | $1$ (Set) | $T=1$ | $Q'$ (Toggle)|
| $S=1, R=0$ | $1$ (Set) | $J=1, K=0$ | $1$ (Set) | | | | |
| $S=1, R=1$ | Invalid | $J=1, K=1$ | $Q'$ (Toggle)| | | | |
### 3.2 Excitation Tables
Indicates the required inputs to transition from a current state $Q$ to a desired next state $Q_{next}$. *Crucial for counter and sequential circuit design.*
| Current ($Q$) | Desired ($Q_{next}$) | $S$ | $R$ | $J$ | $K$ | $D$ | $T$ |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| $0$ | $0$ | $0$ | $X$ | $0$ | $X$ | $0$ | $0$ |
| $0$ | $1$ | $1$ | $0$ | $1$ | $X$ | $1$ | $1$ |
| $1$ | $0$ | $0$ | $1$ | $X$ | $1$ | $0$ | $1$ |
| $1$ | $1$ | $X$ | $0$ | $X$ | $0$ | $1$ | $0$ |
---
## 4. Registers and Shift Registers
A **register** is a group of flip-flops used to store multiple bits of binary data. A **shift register** is capable of shifting binary data left or right.
### 4.1 Four Basic Configurations
1. **SISO (Serial-In Serial-Out)**: Data entered one bit per clock cycle, read out one bit per clock cycle. Needs $N$ clock cycles for loading, $N-1$ for retrieval.
2. **SIPO (Serial-In Parallel-Out)**: Serial input, all outputs available immediately. Needs $N$ clock cycles to load.
3. **PISO (Parallel-In Serial-Out)**: Parallel load (in 1 clock cycle), serial shift out (needs $N-1$ clock cycles).
4. **PIPO (Parallel-In Parallel-Out)**: Data loaded and read simultaneously (1 clock cycle).
### 4.2 Shift Register Counters
* **Ring Counter**: A circular shift register where the output of the last stage ($Q_N$) is connected to the input of the first stage ($D_0$). A single preset '1' circulates.
- Number of states for $N$ flip-flops = $N$.
- Uses simple decoding logic but has a low state density.
* **Johnson Counter (Twisted Ring Counter)**: The inverted output of the last stage ($Q_N'$) is connected to the input of the first stage ($D_0$).
- Number of states for $N$ flip-flops = $2N$.
- Example: A 4-bit Johnson counter counts through $8$ states ($0000 \rightarrow 1000 \rightarrow 1100 \rightarrow 1110 \rightarrow 1111 \rightarrow 0111 \rightarrow 0011 \rightarrow 0001 \rightarrow \text{repeat}$).
---
## 5. Counters
Counters are sequential circuits that cycle through a predefined sequence of states.
### Asynchronous (Ripple) vs. Synchronous Counters
* **Asynchronous Counters**:
- The clock input is connected only to the first flip-flop. Subsequent flip-flops are clocked by the outputs of preceding flip-flops.
- **Propagation Delay accumulates**: $T_{total} = N \cdot t_{pd}$. This limits the maximum operating frequency.
* **Synchronous Counters**:
- All flip-flops are connected to a common clock signal and trigger simultaneously.
- Slower propagation delays are avoided, allowing much higher operating frequencies.
### 5.1 Synchronous Counter Design Methodology
1. **Define State Sequence**: Draw the State Transition Diagram.
2. **Construct State Table**: Show present state ($Q_A, Q_B, ...$) and next state ($Q_A^+, Q_B^+, ...$).
3. **Incorporate Excitation Table**: Determine required input excitations for each flip-flop ($J_A, K_A, ...$) using the Excitation Table.
4. **Solve Excitation Equations**: Use K-maps to minimize input expressions in terms of present states.
5. **Draw the Circuit**: Realize using flip-flops and logic gates.
### 5.2 Synchronous Up/Down Counter
Uses a mode control input $M$ to steer the clock or inputs:
- If $M=0$, it counts UP (e.g., $Q_{next}$ determined by $Q$ terms).
- If $M=1$, it counts DOWN (e.g., $Q_{next}$ determined by $Q'$ terms).
### 5.3 Programmable Counters (Mod-N Counters)
Counters that reset to zero (or load a preset value) after reaching a count $N$.
- **Asynchronous Mod-N**: Uses NAND gate feedback connected to the asynchronous **CLEAR** inputs of the flip-flops. When the binary value corresponding to $N$ appears, the NAND gate output goes Low, resetting the counter to $0$.
- **Synchronous Mod-N**: Incorporates feedback gates directly into the $D$ or $J\text{-}K$ inputs so the reset occurs synchronously on the next clock pulse.
---
## 6. Finite State Machines (FSM): Mealy vs. Moore
Sequential circuits can be represented mathematically as FSMs.
### 6.1 Mealy Machine
- Outputs depend on **both the present state and the current inputs**.
- If inputs change, outputs can change immediately (asynchronously), even without a clock edge.
- Generally requires fewer states than a Moore machine to implement the same logic.
```
Inputs ----+------------------+
| v
| +-------------+ | +------------+
| | Combinational| | | Output |
| | Next-State | +->| Logic |----> Outputs
| | Logic | +------------+
| +-------------+ ^
v | |
+------------------+ |
| v |
| +------------------------------+ |
| | State Register (Memory) |--+
| +------------------------------+
+------------------+
```
### 6.2 Moore Machine
- Outputs depend **only on the present state**.
- Outputs are synchronous with the clock.
- Easier to design and analyze since outputs are stable during input transitions.
```
Inputs ------>+-------------+
| Combinational|
| Next-State |
| Logic |
+-------------+
|
v
+---------------+
| State Register|-----+-----> [Output Logic] ----> Outputs
+---------------+ |
^ |
+-------------+
```
---
## 7. Exam Tips & Common Pitfalls
> [!WARNING]
> - **Self-Starting Counters**: When designing counters, check what happens if the circuit powers up in an unused state (e.g., states $5, 6, 7$ in a Mod-5 counter). A robust design must ensure that the counter eventually enters the valid count cycle (self-starting), rather than getting locked in unused states.
> - **Mealy Output Glitches**: Since Mealy outputs respond directly to inputs, any glitch/noise on the inputs can immediately produce a glitch on the output. Moore outputs are filtered by the state register flip-flops and are glitch-free.
Key Revision Rules & Formulas
- Latches (level-sensitive, transparent) vs. Flip-Flops (edge-triggered).
- Flip-flop characteristics: SR (unstable at 11), JK (toggles at 11, subject to race-around), D (copies input), T (toggles).
- Master-Slave JK: resolves race-around by decoupling input sampling (master, clock high) and output updates (slave, clock low).
- Shift register counters: Ring Counter (N states) vs. Johnson Counter (2N states).
- Synchronous counter design: Present/Next State Table -> Excitation mapping -> K-map minimization -> Logic implementation.
- Finite State Machines (FSM): Mealy outputs depend on state + inputs; Moore outputs depend on state only.
Common Exam Pitfalls
- Unused states lockout: not checking if unused power-up states lead back to the main cycle (self-starting check).
- Mealy output glitches: Mealy machine outputs are sensitive to input noise spikes, unlike Moore machines.
Sample Practice Questions
Question 1: The main difference between a latch and a flip-flop is:
- Latches have no feedback loops.
- Latches are level-sensitive, whereas flip-flops are edge-triggered.
- Flip-flops are combinational, whereas latches are sequential.
- Latches require a high-frequency clock.
Explanation: A latch monitors its inputs and updates its output continuously as long as the enable/clock signal is at a active level. A flip-flop only updates its output at the rising or falling edge of the clock signal.
Question 2: What is the invalid state for an SR Latch?
- $S=0, R=0$
- $S=0, R=1$
- $S=1, R=0$
- $S=1, R=1$
Explanation: When both $S$ and $R$ are active ($1$), both outputs $Q$ and $Q'$ are forced Low simultaneously, violating the complementary relationship $Q = (Q')'$. When inputs go back to $0$, the final state is unpredictable (race condition).
Question 3: The characteristic equation of the SR flip-flop is:
- $Q_{next} = S + R'Q$
- $Q_{next} = S' + RQ$
- $Q_{next} = S + RQ'$
- $Q_{next} = S \oplus R \oplus Q$
Explanation: $Q_{next} = S + R'Q$. If $S=1, R=0$, $Q_{next}=1$. If $S=0, R=1$, $Q_{next}=0$. If $S=0, R=0$, $Q_{next}=Q$. (Note: $SR=0$ must be satisfied).
Question 4: Which flip-flop resolves the invalid state of the SR flip-flop by toggling the output?
- D Flip-Flop
- T Flip-Flop
- JK Flip-Flop
- Master-Slave SR Flip-Flop
Explanation: The JK flip-flop uses feedback connections so that when $J=K=1$, the output toggles to its complement: $Q_{next} = Q'$.
Question 5: The characteristic equation of the JK flip-flop is:
- $Q_{next} = JQ' + K'Q$
- $Q_{next} = J'Q + KQ'$
- $Q_{next} = JQ + K'Q'$
- $Q_{next} = J \oplus K \oplus Q$
Explanation: $Q_{next} = JQ' + K'Q$. When $J=K=1$, $Q_{next} = 1\cdot Q' + 0\cdot Q = Q'$ (toggles). When $J=K=0$, $Q_{next} = 0\cdot Q' + 1\cdot Q = Q$ (holds).
Question 6: The race-around condition occurs in a level-triggered JK flip-flop when:
- $J=0, K=0$
- $J=1, K=1$ and clock pulse width $t_w >$ propagation delay $t_{pd}$ of the gates.
- The clock frequency is too low.
- The supply voltage drops.
Explanation: If the clock pulse remains High ($t_w$) longer than the propagation delay of the gates, the toggled output will feed back and toggle again, repeating continuously and resulting in an unpredictable final state.
Question 7: How does a Master-Slave JK Flip-Flop eliminate the race-around condition?
- By using a delay line.
- By ensuring the slave only updates its state when the clock pulse goes Low, isolating inputs from outputs during the transition.
- By running at lower voltages.
- By disabling the feedback path.
Explanation: The Master-Slave JK FF operates in two steps. The Master accepts inputs when the clock is High, but the Slave output is isolated because it is driven by the inverted clock. When the clock goes Low, the Master is disabled, and the Slave copies the Master's state. The output can change at most once per clock cycle.
Question 8: The characteristic equation of the D flip-flop is:
- $Q_{next} = D$
- $Q_{next} = D'$
- $Q_{next} = DQ + D'Q'$
- $Q_{next} = D \oplus Q$
Explanation: The D (Data or Delay) flip-flop transfers its input $D$ to the output $Q_{next}$ at the clock edge: $Q_{next} = D$.
Question 9: The characteristic equation of the T flip-flop is:
- $Q_{next} = T$
- $Q_{next} = T \oplus Q$
- $Q_{next} = TQ$
- $Q_{next} = T'Q$
Explanation: The T (Toggle) flip-flop holds state if $T=0$ ($Q_{next}=Q$) and complements state if $T=1$ ($Q_{next}=Q'$). This is represented by the XOR gate: $T \oplus Q = TQ' + T'Q$.
Question 10: What are the excitation values $S$ and $R$ required to transition a flip-flop from state $Q=0$ to $Q_{next}=0$?
- $S=0, R=X$
- $S=X, R=0$
- $S=0, R=1$
- $S=1, R=0$
Explanation: To keep a state at $0$, we can either apply a Hold ($S=0, R=0$) or a Reset ($S=0, R=1$). Thus, $S$ must be $0$, while $R$ can be either $0$ or $1$ (represented as Don't Care $X$). Hence, $S=0, R=X$.